Abstract: A dynamic read only memory (ROM) which comprises a memory select precharge section, a memory select section, a memory section, a memory precharge section and a plurality of grounding devices. The ground reference for the pulldown transistors is selectively activated at an appropriate time such that the memory sections are active only for a relatively brief portion of the memory cycle, thereby reducing dc power consumption and simplifying the driver circuit.

Abstract: A circuit is disclosed for separating clock and data signals from a combined data-clock stream derived from a disk. The circuit includes two memories or shift registers which sample the incoming data at alternate portions of a reference clock. The outputs of the registers are applied to a decoder which identifies which of the two registers contains the data portion and which contains the clock portion with the missing clock pattern. That determination, in turn, controls the generation of the synchronization signal for the circuit and also establishes a control signal that selects data from the other of the registers.