Abstract: A pixel data selection device for motion compensated interpolation and a method thereof selects pixel data in adjacent frame/fields. First and second storage portions respectively store first pixel data corresponding to a motion vector of a first frame/field that is obtained by delaying an input frame/field and second pixel data corresponding to the motion vector of a second frame/field that is obtained by delaying the first frame/field one or more times. First and second pixel data extracting portions extract individual pixel data from the first and the second pixel data corresponding to a candidate motion vector. First and second optimum pixel outputting portions output optimum pixel data for motion compensation from the extracted individual pixel data.

Abstract: A pixel data selection device for motion compensated interpolation and a method thereof selects pixel data in adjacent frame/fields. First and second storage portions respectively store first pixel data corresponding to a motion vector of a first frame/field that is obtained by delaying an input frame/field and second pixel data corresponding to the motion vector of a second frame/field that is obtained by delaying the first frame/field one or more times. First and second pixel data extracting portions extract individual pixel data from the first and the second pixel data corresponding to a candidate motion vector. First and second optimum pixel outputting portions output optimum pixel data for motion compensation from the extracted individual pixel data.

Abstract: A sampling rate conversion apparatus and method of converting the sampling rate of an input signal by supplying an interpolation filter with interpolated data obtained by interpolating data based on a prototype filter according to conversion rate as its coefficients. The sampling rate conversion apparatus includes an interpolator interpolating predetermined data based on a prototype filter according to conversion rate to obtain a desired filter coefficient, and a sampling rate converter performing interpolation filtering on an input signal by the filter coefficient supplied from the interpolator. Therefore, coefficients of an interpolation filter adaptable to various conversion rates can be provided without using a large on-chip memory, thereby attaining a superb interpolated version for the input signal.

Abstract: A video decoder has an interfacing function for picture synchronization which can synchronize a decoding and display operation in units the size of a picture. The video decoder includes a transport stream (TS) demultiplexer and an interfacer. The TS demultiplexer is a packet separator for separating packetized elementary stream (PES) packet data of a desired program from a received transport stream (TS).

Abstract: An apparatus for receiving data block-interleaved and multi level/phase modulated data and restoring the block-interleaved multi level/phase modulated data into original data, comprises a demodulation and error correction portion for demodulating and error-correcting data to be received and outputting the modulated and error-corrected data; a synchronization portion for generating a fixed sync position signal, based on the comparison between the data output from the demodulation and error correction portion and stored block sync data; and a block deinterleaver for block-deinterleaving the data which is output from the demodulation and error correction portion according to the fixed sync position signal. The apparatus makes certain that a sync signal for block deinterleaving is identical to a sync signal at the transmission end and performs block deinterleaving even though no error correction is made.

Abstract: A high-speed variable length decoding apparatus independently generates a run-level symbol and decodes the run-level symbol, to thereby variable length decode the variable length coded data at high frequency for signal processing. The variable length decoding apparatus includes a storage and output portion for storing the variable length coded data and outputting the stored variable length coded data by a predetermined data amount in response to a data storage state signal, a run-level table for outputting a run-level symbol which is determined by the data output from the storage and output portion, a memory for storing and outputting the run-level symbol output from the run-level table, in a first-in-first-out manner, and generating the signal indicating a data storage state of its own, and a run-level decoder for run-level decoding the run-level symbol output from the memory.

Abstract: A system for transmitting and receiving video signals compressed into low and high frequency band blocks includes an adaptive modulation circuit and an adaptive demodulation circuit. The adaptive modulation circuit receives the video signal blocks to obtain a block adaptive factor and an index signal ID1, transmits the index signal ID1 to a channel, interpolates the block adaptive factor so as to obtain a picture element adaptive factor, and selects a final adaptive factor f1 from either one of the block adaptive factor or the picture element adaptive factor according to the video signals of the peripheral signal blocks. The adaptive demodulation circuit converts the index signal ID1 into the corresponding block adaptive factor f1, and interpolates the block adaptive factor to produce the picture element adaptive factor, so as to selectively provide the block or picture element factor according to the video signals of the peripheral blocks.

Abstract: A sync restoring apparatus includes a first-in-first-out (FIFO) memory for storing the variable-length-coded data and sequentially outputting a predetermined number of bits of data according to a read signal, a decoder for variable-length-decoding the applied data, outputting the block end signal obtained by the decoding operation, and generating a data request signal every time the number of bits of data used in the decoding operation becomes a predetermined number of bits, an error detector for generating an error signal when the number of the block end signals which are not decoded at the exact variable-length-decoding time is not less than a predetermined limit value based on the data format, and an interfacer coupled to transmit the data applied from the FIFO memory according to the read signal, and if the error signal is not generated in the error detector, generating a read signal according to the data request signal generated from the variable-length-decoder, while if the error signal is generated in

Abstract: A variable-length decoder variable-length-decodes a received variable-length-encoded data. The variable-length-encoded data is bit-stuffed in each data block to create data portions with a predetermined number of bits. Frame start codes representing a start of each frame and mass of macroblock start codes distinguishing between a plurality of masses of macroblocks are inserted into the data. Synchronization of data between frames and masses of macroblocks are accomplished via: a first-in-first-out (FIFO) memory which stores encoded data; a decoder which variable-length-decodes the input data in response to a control signal and generates an end-of-block (EOB) error signal when an EOB is not found; a decoding interface which interfaces between the decoder and a timing controller; and a timing controller which synchronizes decoding by use of start and initialization signals.