Abstract: An in-order issue in-order completion micro-controller comprises a pipeline core comprising in succession a fetch address stage, a program access stage, a decode stage, a first execution stage, a second execution stage, a memory access stage, and a write back stage. The various stages are provided a thread ID such that alternating stages use a first thread ID, and the other stages use a second thread ID. Each stage which requires access to thread ID specific context information uses the thread ID to specify this context information.

Abstract: A process for initializing and booting the CPU of a wireless communication device includes a sequence controller, ROM, a ROM controller, a DMA controller, a wireless front end, a memory, and a remote wireless host which contains the download code. The sequence controller causes the ROM controller initially transfers a Source, a Destination and a Length to the DMA controller, which uses these values to copy the ROM contents into the memory. Thereafter, the sequence controller causes the CPU to start executing the code that has been transferred into memory by the ROM controller, and the CPU thereafter downloads the operating system into memory using the wireless front end, which is receiving an original and duplicate packet from the remote host. Upon completion of the download, the CPU executes the downloaded operating system and begins operation of the device.

Abstract: A wireless signal processor for handling a plurality of wireless sessions comprises a plurality of baseband receivers, one for each session, each receiver producing a digital output, a multiplexer for multiplexing the plurality of digital outputs into a single data stream, a digital signal processor for converting the stream of multiplexed data into a media access controller format, and a media access controller for demultiplexing and framing the stream of data into a plurality of data buffers, one data buffer for each wireless session.

Abstract: The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number comparison. In one embodiment, variably-sized addresses are accommodated by augmenting a portion of the applied address operands to ensure easy access to potential carry bits. A comparator is used for each virtual page number stored in a translation look-aside buffer to quickly determine whether that virtual page number matches the applied address operand sum.

Abstract: A wireless signal processor for handling a plurality of wireless sessions comprises a plurality of baseband receivers, one for each session, each receiver producing a digital output, a multiplexer for multiplexing the plurality of digital outputs into a single data stream, a digital signal processor for converting the stream of multiplexed data into a media access controller format, and a media access controller for demultiplexing and framing the stream of data into a plurality of data buffers, one data buffer for each wireless session.

Abstract: Scan chain routing efficiency is improved in an integrated circuit (IC) such as an application specific integrated circuit (ASIC) by defining flip flop groupings prior to place and route. A flip flop grouping specifies the arrangement of multiple flip flops and the scan chain routing through those flip flops. The predetermined flip flop arrangement of the flip flop grouping then prevents undesirable flip flop placements during place and route. The flip flop grouping therefore minimizes the layout impacts of scan insertion while simplifying the place and route process. Different flip flop groupings can be used in a single IC design, and flip flop groupings can be combined with individual flip flops in the IC layout. A flip flop grouping can include control logic for the flip flops. Clock gating logic can be offloaded from the flip flops into the control logic to further improve layout efficiency.

Abstract: The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number comparison. In one embodiment, variably-sized addresses are accommodated by augmenting a portion of the applied address operands to ensure easy access to potential carry bits. A comparator is used for each virtual page number stored in a translation look-aside buffer to quickly determine whether that virtual page number matches the applied address operand sum.

Abstract: A method for fabricating IC devices including both rising edge-triggered circuits (e.g., flip-flops or latches) and falling edge-triggered circuits in which a clock signal line is selectively inverted by an on-chip clock signal inverting circuit and applied to one or the other circuit types during test modes. The clock signal inverting circuit is implemented as a two-input exclusive-OR gate, or using a multiplexer. The method includes placing and routing the selected circuit type (i.e., rising or falling edge) such that clock skew is minimized.

Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Abstract: In a multi-tasking computing system environment, one program is halted and context switched out so that a processor may context switch in a subsequent program for execution. Processor state information exists which reflects the state of the program being context switched out. Storage of this processor state information permits successful resumption of the context switched out program. When the context switched out program is subsequently context switched in, the stored processor information is loaded in preparation for successfully resuming the program at the point in which execution was previously halted. Although, large areas of memory can be allocated to processor state information storage, only a portion of this may need to be preserved across a context switch for successfully saving and resuming the context switched out program.

Abstract: A method and apparatus for providing a program counter value within a central processing unit is described. A program counter value comprises n bits and has to be increased by one of a plurality of different fixed increment values. Therefore, an upper partial content of the current program counter value and its value incremented by 1 is provided. Also, a plurality of lower partial contents of the current program counter value incremented by one of the plurality of fixed increment values, respectively are provided, whereby a carry bit is provided. One of the plurality of incremented lower partial contents is selected depending on said respective carry bit. Upper and lower contents are then combined to form a plurality of new program counter values. Upon receiving of control information to select a final increment value one of said new program counter values will be selected.

Abstract: A method is provided for writing a scalar value to a vector V1 without reading the vector from a storage device. A scalar value to be written into the vector at a specified position and a scalar value (index) representing such position are read from a storage device into an Arithmetic Logic Unit (ALU) of a vector processor. The ALU then generates another vector V2 having multiple copies of the scalar value to be written into V1. ALU also generates a mask representing the index. The vector V2 is then delivered to the storage storing V1, but the mask is applied so that only one or more, but not all, copies of the scalar value are written from V2 to the storage. The rest of the vector V1 remains unchanged. The invention reduces register file read contention. Furthermore, if the updated V1 (i.e. V1 having the scalar value) is to be used in the next instruction, a copy of V1 is read from the storage and is updated from V2 and the mask, simultaneously with V1 being updated in the storage.

Abstract: A N-byte vector processor is provided which can emulate 2N-byte processor operations by executing two N-byte operations sequentially. By using N-byte architecture to process 2N-byte wide data, chip size and costs are reduced. One embodiment allows 64-byte operations to be implemented with a 32-byte vector processor by executing a 32-byte instruction on the first 32-bytes of data and then executing a 32-byte instruction on the second 32-bytes of data. Registers and instructions for 64-byte operation are emulated using two 32-byte registers and instructions, respectively, with some instructions requiring modification to accommodate 64-byte operations between adjacent elements, operations requiring specific element locations, operations shifting elements in and out of registers, and operations specifying addresses exceeding 32 bytes.

Abstract: An integrated multiprocessor architecture simplifies synchronization of multiple processing units. The multiple processing units constitute a general-purpose or control processor and a vector processor which has a single-instruction-multiple-data (SIMD) architecture so that multiple parallel processing units in the vector processor all complete an instruction simultaneously and do not require software synchronization. The control control processor controls the vector processor and creates a fork in a program flow by starting the vector processor. An instruction set for the control processor includes special instructions that enable the control processor to access registers of the vector processor, start or halt execution by the vector processor, and test flags written by the vector processor to indicate completion of tasks.

Abstract: A cache system supports a re-sizable software-managed fast scratch pad that is implemented as a cache-slice. A processor register indicates the size and base address of the scratch pad. Instructions which facilitate use of the scratch pad include a prefetch instruction which loads multiple lines of data from external memory into the scratch pad and a writeback instruction which writes multiple lines of data from the scratch pad to external memory. The prefetch and writeback instructions are non-blocking instructions to allow instructions following in the program order to be executed while a prefetch or writeback operation is pending.

Abstract: An apparatus coupled to a requesting unit and a memory. The apparatus includes a data path and a request control circuit. The data path is coupled to the requesting unit and the memory. The data path is for buffering a vector. The vector includes multiple data elements of a substantially similar data type. The request control circuit is coupled to the data path and the requesting unit. The request control circuit is for receiving a vector memory request from the requesting unit. The request control circuit services the vector memory request by causing the transference of the vector between the requesting unit and the memory via the data path.

Abstract: An instruction decoder in a processor decodes an instruction by creating a decode buffer entry that includes global fields, operand fields, and a set of micro-instructions. Each micro-instruction represent an operation that an associated execution unit can execute in a single clock cycle. A scheduler issues the micro-instructions from one or more entries to the execution units for possible parallel and out-of-order execution. Each execution unit completes an operation, typically, in one clock cycle and does not monitor instructions that may block a pipeline. The execution units do not need separate decoding for multiple stages. One global field indicates which micro-instructions are execute first. Further, micro-instructions have fields that indicate an execution sequence. The scheduler issues operations in the order indicated by the global fields and the micro-instructions. When the last operation for an instruction is completed, the instruction is retired and removed from the decode buffer.

Abstract: A wide data width processor has an execution unit including an aligner that aligns data for load/store instructions and shifts or rotates data for arithmetic logic instructions. Use of the same circuitry and execution unit for these different types of instructions reduces overall circuit size because alignment circuitry need not be repeated, once in a load/store unit and once in an arithmetic logic unit.

Abstract: An instruction fetch unit includes a program buffer for sequential instructions being decoded and a target buffer for an instruction sequence including the target of the next branch instruction. Scan logic coupled to the program buffer scans the program buffer for branch instructions. A target for the first branch instruction is determined and a request to external memory fills the target buffer with a sequence of instructions including a target instruction before sequential decoding reaches the branch instruction. If the branch is subsequently taken, the instructions from the branch target buffer are transferred to the program buffer. The program buffer may be divided into a main and a secondary buffer that have the same size as the target buffer, and an instruction bus between the instruction fetch unit and external memory is sufficiently wide to fill the main, secondary, or target buffer in a single write operation.

Abstract: A superscalar processor includes an execution unit that executes load/store instructions and an execution unit that executes arithmetic instruction. Execution pipelines for both execution units include a decode stage, a read stage that identify and read source operands for the instructions and an execution stage or stages performed in the execution units. For store instructions, reading store data from a register file is deferred until the store data is required for transfer to a memory system. This allows the store instructions to be decoded simultaneously with earlier instructions that generate the store data. A simple antidependency interlock uses a list of the register numbers identifying registers holding store data for pending store instructions.