Patents by Inventor Herbert Benzinger
Herbert Benzinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7482644Abstract: Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.Type: GrantFiled: February 18, 2005Date of Patent: January 27, 2009Assignee: Infineon Technologies AGInventors: Georg Erhard Eggers, Stephan Schröder, Manfred Pröll, Herbert Benzinger
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Patent number: 7443713Abstract: An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.Type: GrantFiled: January 13, 2006Date of Patent: October 28, 2008Assignee: Infineon Technologies AGInventors: Stephan Schröder, Herbert Benzinger, Georg Erhard Eggers, Manfred Pröll, Jörg Kliewer
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Patent number: 7266027Abstract: An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.Type: GrantFiled: September 27, 2005Date of Patent: September 4, 2007Assignee: Infineon Technologies AGInventors: Ralf Schneider, Stephan Schröder, Manfred Pröll, Herbert Benzinger
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Publication number: 20070176255Abstract: An integrated circuit arrangement comprises at least one one-time programmable storage element, which can be electrically deactivated, having at least one electrically conductive or semi-conductive nanotube or at least one electrically conductive or semi-conductive nanowire.Type: ApplicationFiled: January 31, 2006Publication date: August 2, 2007Inventors: Franz Kreupl, Georg Eggers, Herbert Benzinger, Ingo Bormann, Martin Schnell
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Patent number: 7248536Abstract: A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that the word line segment (12) is otherwise activated. The second line (22) can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (12), the word line segment can be driven via a switching element (17), which couples the word line segment to the second line (22), without the complementary switching element (16) of the driver segment (20) having to be used for deactivation.Type: GrantFiled: October 6, 2005Date of Patent: July 24, 2007Assignee: Infineon Technologies AGInventors: Stephan Schroeder, Arndt Gruber, Manfred Proell, Herbert Benzinger
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Patent number: 7206238Abstract: A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or a charge quantity (Q) which is fed to the word line (12) or conducted away from the word line segment (12) as a result of this is measured. If, upon activation or deactivation of a word line segment (12), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment (12) has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments (12) can be replaced by redundant word lines.Type: GrantFiled: September 1, 2005Date of Patent: April 17, 2007Assignee: Infineon Technologies AGInventors: Joerg Kliewer, Herbert Benzinger, Stephan Schroeder, Manfred Proell
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Publication number: 20070047355Abstract: A method for detecting a leakage current in a bit line of a semiconductor memory is disclosed. In one embodiment, the method includes isolating the connection of a sense amplifier from a bit line via an isolation transistor, reading out a memory cell to the bit line, waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes the voltage on the bit line within the delay time. The sense amplifier is short circuited with the bit line via the isolation transistor. The voltage on the bit line is collected by the sense amplifier, and compared with a reference voltage so as to detect the leakage current.Type: ApplicationFiled: August 28, 2006Publication date: March 1, 2007Applicant: QIMONDA AGInventors: Herbert Benzinger, Tobias Graf, Joerg Kliewer, Manfred Proell, Stephan Schroeder
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Patent number: 7180820Abstract: An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.Type: GrantFiled: May 27, 2005Date of Patent: February 20, 2007Assignee: Infineon Technologies AGInventors: Jörg Kliewer, Herbert Benzinger, Manfred Pröll, Stephan Schröder
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Patent number: 7120074Abstract: A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.Type: GrantFiled: August 4, 2004Date of Patent: October 10, 2006Assignee: Infineon Technologies AGInventors: Manfred Proell, Herbert Benzinger, Manfred Dobler, Joerg Kliewer
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Patent number: 7102912Abstract: An integrated semiconductor memory device includes a memory cell array (B1) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit (100) configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET1) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A10) that applies a mid-voltage (VBLEQ), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (VBLEQ) is shortened.Type: GrantFiled: March 4, 2005Date of Patent: September 5, 2006Assignee: Infineon Technologies, AGInventors: Herbert Benzinger, Jörg Kliewer, Manfred Pröll, Stephan Schröder
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Publication number: 20060193168Abstract: An integrated semiconductor memory device includes memory cells each with a selection transistor and a storage capacitor. Memory cells of this type are usually read by the potential of the bit line to which the memory cell is connected being compared in a sense amplifier with the potential of a complementary, second bit line and a voltage difference identified being amplified. The semiconductor memory according to the invention provides for that capacitor electrode which is not connected to the selection transistor to be connected to the complementary, second bit line. As a result, for an operating voltage with the same magnitude, larger quantities of charge can be stored in the storage capacitor since now the two mutually spread potentials output by the sense amplifier are used for biasing the storage capacitor.Type: ApplicationFiled: January 13, 2006Publication date: August 31, 2006Inventors: Stephan Schroder, Herbert Benzinger, Georg Eggers, Manfred Proll, Jorg Kliewer
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Publication number: 20060120176Abstract: An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.Type: ApplicationFiled: September 27, 2005Publication date: June 8, 2006Inventors: Ralf Schneider, Stephan Schroder, Manfred Proll, Herbert Benzinger
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Publication number: 20060083100Abstract: A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that the word line segment (12) is otherwise activated. The second line (22) can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (12), the word line segment can be driven via a switching element (17), which couples the word line segment to the second line (22), without the complementary switching element (16) of the driver segment (20) having to be used for deactivation.Type: ApplicationFiled: October 6, 2005Publication date: April 20, 2006Inventors: Stephan Schroeder, Arndt Gruber, Manfred Proell, Herbert Benzinger
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Publication number: 20060056266Abstract: A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or a charge quantity (Q) which is fed to the word line (12) or conducted away from the word line segment (12) as a result of this is measured. If, upon activation or deactivation of a word line segment (12), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment (12) has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments (12) can be replaced by redundant word lines.Type: ApplicationFiled: September 1, 2005Publication date: March 16, 2006Inventors: Joerg Kliewer, Herbert Benzinger, Stephan Schroeder, Manfred Proell
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Patent number: 6999355Abstract: A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory has a first voltage generator circuit for generating a supply voltage for application to the read/write amplifier during an assessment and amplification operation and a second voltage generator circuit for generating a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier. A temperature detector circuit, which is connected to the first voltage generator circuit, is used to detect a temperature of the memory and interacts with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier in a manner depending on a temperature of the memory.Type: GrantFiled: May 10, 2004Date of Patent: February 14, 2006Assignee: Infineon Technologies AGInventors: Herbert Benzinger, Koen Van der Zanden, Stephan Schröder, Manfred Pröll
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Publication number: 20050281118Abstract: An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.Type: ApplicationFiled: May 27, 2005Publication date: December 22, 2005Inventors: Jörg Kliewer, Herbert Benzinger, Manfred Pröll, Stephan Schröder
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Patent number: 6970389Abstract: An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals of the memory cells, and a sense amplifier connected to bit lines of a bit line pair at one end of the bit line pair. In an activated state during a memory access, at least one activatable isolation circuit which is switched into one of the bit line pairs can isolate a part of the bit line pair, which is more remote from the sense amplifier from the sense amplifier. As a result, the effective capacitance of the bit lines can be significantly reduced during the memory access.Type: GrantFiled: January 15, 2004Date of Patent: November 29, 2005Assignee: Infineon Technologies, AGInventors: Manfred Proell, Stephan Schroeder, Herbert Benzinger, Aurel von Campenhausen
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Publication number: 20050195638Abstract: An integrated semiconductor memory device includes a memory cell array (B1) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit (100) configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET1) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A10) that applies a mid-voltage (VBLEQ), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (VBLEQ) is shortened.Type: ApplicationFiled: March 4, 2005Publication date: September 8, 2005Inventors: Herbert Benzinger, Jorg Kliewer, Manfred Proll, Stephan Schroder
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Publication number: 20050194614Abstract: Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.Type: ApplicationFiled: February 18, 2005Publication date: September 8, 2005Inventors: Georg Eggers, Stephan Schroder, Manfred Proll, Herbert Benzinger
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Publication number: 20050133785Abstract: The invention relates to a method and a device (1, 11, 21) for detecting the overheating of a semiconductor device, comprising a temperature measuring means (3, 13, 23) that changes its electrical conductivity when the temperature of the semiconductor device changes.Type: ApplicationFiled: November 24, 2004Publication date: June 23, 2005Applicant: Infineon Technologies AGInventors: Georg Eggers, Norbert Wirth, Herbert Benzinger, Thomas Huber