Abstract: The invention relates to an arrangement (10) and a method for adjusting the slope times of one or more drivers (90) in such a way that the adjustment is essentially independent of external conditions. The invention also relates to a driver circuit. The arrangement (10) is provided with a device (20) for detecting the time history of an output voltage that is output and supplied to a load (12) by means of the driver/s (90). The measured time values are converted into an output voltage value in a device (36) for converting the measured time history of the output voltage. Moreover, a device (40) for generating a reference voltage value is provided. The device (40) is connected to a device (60) for predetermining a desired slope time for the driver/s (90), whereby the slope time is essentially independent of external conditions.

Abstract: The invention relates to an arrangement (10) and a method for adjusting the slope times of one or more drivers (90) in such a way that the adjustment is essentially independent of external conditions. The invention also relates to a driver circuit. The arrangement (10) is provided with a device (20) for detecting the time history of an output voltage that is output and supplied to a load (12) by means of the driver/s (90). The measured time values are converted into an output voltage value in a device (30) for converting the measured time history of the output voltage. Moreover, a device (40) for generating a reference voltage value is provided. Said device (40) is connected to a device (60) for predetermining a desired slope time for the driver/s (90), whereby said slope time is essentially independent of external conditions.

Abstract: A device for reducing the electromagnetic emission in integrated circuits having driver stages reduces the electromagnetic emission of an integrated circuit without requiring an increase in the blocking capacitance in the process. This is achieved by combining driver stages which do not switch simultaneously to form driver groups, and special wiring of a plurality of blocking capacitors.

Abstract: The integrated circuit with programmable pad driver involves an integrated circuit (IS1) with at least one pad driver that has a programming unit (PE) and a plurality of sub-drivers (T1 . . . Tm). A specific driver intensity and edge steepness of the pad driver can be set in that a corresponding plurality of sub-drivers connected to a common terminal contact (PAD) at their output side are activated/deactivated dependent on output signals (P1 . . . Pm) of the programming unit.

Abstract: The arrangement stores, in a knowledge base memory (KBM), important (dominant) and less important rules such that they can be distinguished from one another. From a rule weighting (gi) and from an aggregated rule weighting (Gi-1) is formed. The unsharp OR linking has a unit (BSUM) for forming a limited sum, if an important rule is present, and has a unit (MAX) for forming a maximum if a less important rule is present. In this way it is ensured that each important rule, for which the rule evaluation results in a rule weighting greater than zero, has an effect on the sharp value of the relevant output variable.

Abstract: A defuzzification device in which, depending on selection signals (FA1, FA2) and aggregated regulation weights (.gamma.), either in a maximum process a first/last maximum value at which an associated aggregated regulation weight is a maximum is selected as the sharp output value (g) and an activation signal (ENGARZ) is formed or, as an alternative, in a first or second center of gravity process (COG12) a sharp output value (g) is formed from center of gravity coordinates (S.sub..nu.) and aggregated regulation weights (.gamma..sub..nu.), alone or additionally using area measurement figures (F.sub..nu.), adders (ADD1, ADD2) with a register (Z-Reg, N-Reg) connected downstream in each case, a multiplier (MULT) and a divider (DIV) being able to be used advantageously both for the first and for the second center of gravity process, and one of the adders (ADD2) being used for the formation of the activation signal (ENGARZ), if a defuzzification is being carried out according to the maximum process.

Abstract: Circuit (SPSA) has a processing unit (VE) with an electrically erasable and electrically programmable read-only memory (EEPROM), a classification unit (KE) and an interface unit (EIF) for the read-only memory. The processing unit (VE) reads out from the read-only memory (EEPROM) instructions and/or data which have been automatically programmed in by a classification unit (KE) and an interface unit (EIF), as a function of input values (E) and/or internal values (ED, S) and/or output values (A) of the processing unit (VE). The processing unit may in this case take the form of a fuzzy controller or else a customary microprocessor. The advantage achieved hereby is, in particular, that the arrangement automatically adapts itself to the variance in structure (type diversity) and variance in time (ageing, wear) of a product and consequently the circuit has a wider range of applications and can be used optimally for a longer period of time.

Abstract: An apparatus for inference formation and defuzzification has an arithmetic unit, a memory/register unit, and a controller, wherein crisp output signals can be formed from weighting factors and dimensional scaling numbers dependent on control signals with a weighting factor being provided for each linguistic value of the output variables, the dimensional numbers characterizing the membership functions of the linguistic values of the output variables. The apparatus exhibits high processing speed and requires only low storage space, particularly given definitions of the crisp output signal of greater than or equal to eight bits.

Abstract: The invention relates to a multi-stage digital logic circuit in which, for example, it is possible to assign an output word (C0, . . . , C3) a minimum of two input words (A0, . . . , A3; B0, . . . , B3), and in which it is possible to form output bits (for example C3) having a high place value before output bits (for example C2, C1 or C0) having a lower place value.

Abstract: In a fuzzy logic controller, numbers (NI) for linguistic values of the input signal (I1) and first and further parts of input relevance functions (ZL, ZH) of the input signal (I1) can be stored per input signal (I1 . . . I4) in an input memory (I1MEM . . . I4MEM). The numbers for the linguistic values can be fed directly and via incrementing devices (INC1 . . . INC4) to a regulating decoder (RDEC) through a number multiplexer (MUX1a . . . MUX4a), the regulating decoder supplying addresses for a downstream output memory (OMEM). An output signal of the output memory (OMEM) can be fed directly and the first and further parts of the input relevance functions can be fed via relevance function multiplexers (MUX1b . . . MUX4b) to a minimum/maximum circuit (MINMAX). The fuzzy logic controller is distinguished in particular by a very low storage space requirement and is therefore suitable in particular for fuzzy logic controllers with on-chip memories.

Abstract: A fuzzy logic controller is composed of a fuzzification circuit (FUZ), a rule decoder (RDEC), a rule evaluation circuit (RA), an inference circuit (INF), a defuzzification circuit (DFUZ) and a sequencer (CTRL). Numbers (NA) for linguistic values of the output variables together with selection signals (SM) for the definition of the input variables affected by the respective rule formed in the rule decoder and are supplied to the rule evaluation circuit in addition to the values (ME) of the affiliation functions for the linguistic values of the input variables. A weighting signal (G) is generated in the rule evaluation circuit for every linguistic value of the output variables. The advantages obtainable are the high processing speed, the low requirement for chip area, the variable rule format and the selection possibility of different operation modes in the rule evaluation circuit, the inference circuit and the defuzzification circuit.