Abstract: A parallel computing system comprising N blocks of processors, where N is an integer greater than 1. Each block of the N blocks of processors contains M processors, where M is an integer greater than 1. Each processor includes an arithmetic logic unit (ALU), a local memory and an input/output (I/O) interface. The computing system also contains a control means, connected to each of the M processors, for providing identical instructions to each of the M processors, and a host means, coupled to each of the control means within the N blocks of processors. The host means selectively organizes the control means of each of the N blocks of M processors into at least two groups of P blocks of M processors, P being an integer less than or equal to N. In operation, the host means causes the control means within each group of P blocks of M processors to provide each group of P blocks of M processors respectively different identical processor instructions.

Abstract: A processor for use in a parallel computing system. The processor contains: a memory for storing operand values; an arithmetic logic unit (ALU) for performing arithmetic logic operations on operand values; a multiplier, separate from the ALU and coupled to the memory, for generating arithmetic products of a first operand value and a second operand values; and a match unit, separate from the ALU and coupled to the memory, for detecting matches between a predetermined bit pattern and a sequence of bits retrieved from the memory. The match unit also generates a count value indicating a number of detected matches between the predetermined bit pattern and subsequences of bits within the sequence of bits. The first operand value contains the bit pattern and the second operand contains the sequence of bits.

Abstract: A video signal processor includes a stored-program controller which concurrently reads two instruction values from a program memory during each instruction cycle. The next instruction used by the video signal processor is selected from between these two values. If the current instruction indicates a conditional branch operation, the value of one of a plurality of conditions internal to the video signal processor determines which of these two instructions is selected. Otherwise, a value provided by the current instruction itself determines which of the two instructions is selected. This configuration of the stored program controller implements a conditional branch facility in which there is no delay in fetching an instruction for either value of the selected condition.