Abstract: A radiation imaging system comprising a scintillator, an imager array, and a lamination layer. Lamination layer bonds and optically couples scintillator to imager array. Lamination layer is comprised of a lamination material that is substantially free from void spaces. Radiation imaging system fabrication comprises the steps of disposing lamination layer between a light imager and a scintillator to form a subassembly. Light imager comprises imager array, an imaging plate surface and a plurality of contact pads. Additional steps include subjecting subassembly to a vacuum; heating subassembly to a bonding temperature, exerting a bonding force on subassembly, maintaining the vacuum, the bonding temperature and the bonding force until light imager is bonded to the scintillator and the lamination layer is comprised of lamination material that is substantially free from void spaces.

Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

Abstract: In the present invention an adhesive composition is provided. The adhesive composition includes epoxidized cashew nutshell liquid, a catalyst, and diglycidyl ether of bisphenol A. The invention may further include at least one additive selected from the group including curing agents, bonding enhancers, hardeners, flexibilizers, tackifiers, and mixtures thereof.

Abstract: A radiation imaging system comprising a scintillator, an imager array, and a lamination layer. Lamination layer bonds and optically couples scintillator to imager array. Lamination layer is comprised of a lamination material that is substantially free from void spaces. Radiation imaging system fabrication comprises the steps of disposing lamination layer between a light imager and a scintillator to form a subassembly. Light imager comprises imager array, an imaging plate surface and a plurality of contact pads. Additional steps include subjecting subassembly to a vacuum; heating subassembly to a bonding temperature, exerting a bonding force on subassembly, maintaining the vacuum, the bonding temperature and the bonding force until light imager is bonded to the scintillator and the lamination layer is comprised of lamination material that is substantially free from void spaces.

Abstract: A current limiting device utilizes an electrically conductive composite material and an inhomogeneous distribution of resistance structure. The electrically conductive composite material comprises an organic binder portion comprising a high Tg epoxy and a low viscosity polyglycol epoxy; at least one epoxy curing agent; and a conductive powder.

Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide.

Abstract: A low dielectric constant printed circuit board includes: a low dielectric constant porous polymer layer having holes therethrough, the porous layer having pores; and a patterned metallization layer over surfaces of the low dielectric constant porous polymer layer and surfaces of the holes, the patterned metallization layer not significantly protruding into the pores of the porous layer.

Abstract: A multi-chip electronics module is provided which utilizes benzocyclobutene as a laminate adhesive for bonding the upper dielectric films in a high density interconnect structure. The benzocyclobutene thermosetting polymer is spin coated on a polyimide film, and baked at low temperature to remove any solvent to leave a B-staged coating on the polyimide film. The composite film can be laminated to an underlying electrical structure using a vacuum laminator and heat. As the heat is applied, the BCB layer softens, flows and then cures to bond the polyimide film to the underlying electrical structure.

Abstract: A method for making an HDI-connected circuit is described, which in a simple manner allows an air pocket, space, gap, or bubble to be formed over pressure- or dielectric-sensitive portions of a semiconductor chip. The method applies a layer of uncured adhesive over a dielectric film, and also over any electrical conductors deposited on the film. The adhesive is exposed through a mask to a laser beam, which selectively vaporizes the adhesive in the exposed regions, to define the air pocket region. The semiconductor chips are applied, electrode-side down, on the adhesive, with the sensitive regions registered with the pockets. The adhesive is cured, and conductive vias are formed through the dielectric film and the adhesive to make contact with the electrodes of the semiconductor chips. Other layers of HDI interconnect are then applied over the dielectric film, and interconnected by vias, if needed.

Abstract: A method includes applying a first seed layer extending over a horizontal surface and via sidewalls of a dielectric material and exposed underlying contact metallization; removing at least some of the first seed layer from the contact metallization and the horizontal surface while leaving a sufficient amount of the first seed layer on the sidewalls as a catalyst for subsequent application of a third seed layer; sputtering a second seed layer over the contact metallization and the horizontal surface; using an electroless solution to react with the first seed layer and apply the third seed layer over the sidewalls; and electroplating an electroplated layer over the second and third seed layers.

Abstract: A current limiting device utilizes an electrically conductive composite material and an inhomogeneous distribution of resistance structure. The electrically conductive composite material comprises an organic binder portion comprising a high Tg epoxy and a low viscosity polyglycol epoxy; at least one epoxy curing agent; and a conductive powder.

Abstract: A method includes applying a first seed layer extending over a horizontal surface and via sidewalls of a dielectric material and exposed underlying contact metallization; removing at least some of the first seed layer from the contact metallization and the horizontal surface while leaving a sufficient amount of the first seed layer on the sidewalls as a catalyst for subsequent application of a third seed layer; sputtering a second seed layer over the contact metallization and the horizontal surface; using an electroless solution to react with the first seed layer and apply the third seed layer over the sidewalls; and electroplating an electroplated layer over the second and third seed layers.

Abstract: For fully testing and burning-in an integrated circuit chip before it is incorporated into a high density interconnect or other standard hybrid bare chip circuit, a temporary test substrate having pins extending therethrough holds the chip within a cavity. Chip pads are electrically connected with the pins to create a package that can be tested using commercially available testing and burn-in devices. After testing, the chip is retrieved from the test structure undamaged. In using HDI techniques to interconnect the chip with the pins, metal-filled vias in a polymer layer overlying the temporary test substrate electrically connect the chip to the pins through a metal interconnect pattern on the polymer layer. In another embodiment, the chip is interconnected with the pins through wire bonds. Metal-filled vias pass through an insulative coating on the chip and make electrical contact with the chip pad.

Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide.

Abstract: A method for fabricating a low dielectric constant printed circuit board includes dispersing an additive material in a low dielectric constant porous polymer layer; providing holes through the low dielectric constant porous polymer layer; applying a metallization layer over surfaces of the low dielectric constant porous polymer layer and surfaces of the holes; patterning the metallization layer; and removing the additive material from the low dielectric constant porous polymer layer. The removal of the additive material can be accomplished by sublimation, evaporation, and diffusion.

Abstract: A multi-chip module is provided which utilizes benzocyclobutene as a laminate adhesive for bonding the upper dielectric films in a high density interconnect structure. The benzocyclobutene thermosetting polymer is spin coated on a polyimide film, and baked at low temperature to remove any solvent to leave a B-staged coating on the polyimide film. The composite film can be laminated to an underlying electrical structure using a vacuum laminator and heat. As the heat is applied, the BCB layer softens, flows and then cures to bond the polyimide film to the underlying electrical structure.