Patents by Inventor Herbert Tsai
Herbert Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9638740Abstract: A test system with rotational test arms for testing semiconductor components includes a transport device, a first test socket, a second test socket, a first test arm, and a second test arm. The first test socket and the second test socket are electrically connected to different test signals respectively and correspond to the first test arm and the second test arm. The first test arm and the second test arm test arms operate rotationally to carry and place the semiconductor components to the transport device, the first test socket and the second test socket, so the test time is improved.Type: GrantFiled: October 8, 2013Date of Patent: May 2, 2017Assignee: CHROMA ATE INC.Inventors: Chien-Ming Chen, Herbert Tsai, Chin-Yi Ou Yang
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Publication number: 20140103954Abstract: A test system with rotational test arms for testing semiconductor components includes a transport device, a first test socket, a second test socket, a first test arm, and a second test arm. The first test socket and the second test socket are electrically connected to different test signals respectively and correspond to the first test arm and the second test arm. The first test arm and the second test arm test arms operate rotationally to carry and place the semiconductor components to the transport device, the first test socket and the second test socket, so the test time is improved.Type: ApplicationFiled: October 8, 2013Publication date: April 17, 2014Applicant: CHROMA ATE INC.Inventors: Chien-Ming CHEN, Herbert TSAI, Chin-Yi OU YANG
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Patent number: 7545158Abstract: A method for testing System-In-Package (SIP) devices each having a plurality of electrical contacts is described. The method and apparatus utilizes industry standard JEDEC trays and tests at least a predetermined portion of all devices in such trays at the same time.Type: GrantFiled: April 12, 2007Date of Patent: June 9, 2009Assignee: Chroma ATE Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Patent number: 7535214Abstract: Apparatus for testing System-In-Package (SIP) devices each having a plurality of electrical leads is described. The apparatus utilizes industry standard JEDEC trays and tests at least a predetermined portion of all devices in such trays at the same time. The apparatus comprises a test hive comprising: a plurality of test circuits corresponding in number to at least a predetermined number of cells in the tray; and a plurality of groups of test contacts, each group is coupled to one of the test circuits and is oriented to engage the plurality of electrical contacts of a SIP device disposed in a corresponding one of the cells. The test hive is operable to simultaneously, electrically test at least a predetermined number of the number of the SIP devices in each tray engaged by the hive without removing the SIP devices from the tray.Type: GrantFiled: April 12, 2007Date of Patent: May 19, 2009Assignee: Chroma Ate IncInventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Patent number: 7518356Abstract: Apparatus for testing System-In-Package (SIP) devices each having a plurality of electrical contacts is described. The apparatus comprises a JEDEC standard tray receiving apparatus comprising a plurality of tray aligners to align the tray into a predetermined position to account for dimensional tolerances of the tray. The apparatus further comprises a test assembly proximate the tray receiving apparatus. The assembly comprises; a plurality of test circuits corresponding in number to the number of cells in the tray, a plurality of groups of test contacts, each of group of the test contacts being coupled to one of the test circuits and being oriented to engage a plurality of electrical contacts of a SIP device disposed in a corresponding one of the cell, the plurality of test circuits being operable to simultaneously, electrically test a predetermined number of SIP devices in a JEDEC standard tray engaged by the receiving apparatus without removing the SIP devices from the tray.Type: GrantFiled: April 12, 2007Date of Patent: April 14, 2009Assignee: Chroma Ate Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Patent number: 7518357Abstract: Apparatus for testing micro SD devices each having a plurality of electrical leads is described. The apparatus utilizes industry standard JEDEC trays and tests all devices in such trays at the same time. The apparatus comprises a test hive comprising: a plurality of test circuits corresponding in number to at least a predetermined number of cells in the tray; and a plurality of groups of test contacts, each group is coupled to one of the test circuits and is oriented to engage the plurality of electrical contacts of a micro SD device disposed in a corresponding one of the cells. The test hive is operable to simultaneously, electrically test at least a predetermined number of the number of the micro SD devices in each tray engaged by the hive without removing the micro SD devices that did pass electrical testing until a tray of electrically tested micro SD devices is fully populated with micro SD devices that did pass electrical testing.Type: GrantFiled: April 12, 2007Date of Patent: April 14, 2009Assignee: Chroma Ate Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Patent number: 7514914Abstract: Apparatus for testing System-In-Package (SIP) devices each having a plurality of electrical leads is described. The apparatus utilizes industry standard JEDEC trays and tests all devices in such trays at the same time. The apparatus of the illustrative embodiment comprises a test hive comprising: a plurality of test circuits corresponding in number to the number of cells in the tray; and a plurality of groups of test contacts, each of the groups of the test contacts being coupled to one of the test circuits and being oriented to engage the plurality of electrical contacts of SIP device disposed in a corresponding one of the cells, the test hive being operable to simultaneously, electrically test all of the SIP devices in each tray engaged by the hive without removing the SIP devices from the tray.Type: GrantFiled: April 12, 2007Date of Patent: April 7, 2009Assignee: Chroma Ate IncInventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Patent number: 7489156Abstract: A method and apparatus for testing micro SD devices each having a plurality of electrical leads is described. The method and apparatus utilizes industry standard JEDEC trays and tests all devices in such trays at the same time.Type: GrantFiled: April 12, 2007Date of Patent: February 10, 2009Assignee: Chruma Ate Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Patent number: 7489155Abstract: A method for testing System-In-Package (SIP) devices such as micro SD devices each having a plurality of electrical leads is described. The method utilizes industry standard JEDEC trays and tests all devices in such trays at the same time.Type: GrantFiled: April 12, 2007Date of Patent: February 10, 2009Assignee: Chroma Ate IncInventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Patent number: 7443190Abstract: A method for testing micro SD devices each having a plurality of electrical leads is described. The method utilizes industry standard JEDEC trays and tests at least a predetermined portion of the devices in such trays at the same time.Type: GrantFiled: April 12, 2007Date of Patent: October 28, 2008Assignee: Chroma Ate IncInventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Publication number: 20080252314Abstract: Apparatus for testing System-In-Package (SIP) devices each having a plurality of electrical leads is described. The apparatus utilizes industry standard JEDEC trays and tests at least a predetermined portion of all devices in such trays at the same time. The apparatus comprises a test hive comprising: a plurality of test circuits corresponding in number to at least a predetermined number of cells in the tray: and a plurality of groups of test contacts, each group is coupled to one of the test circuits and is oriented to engage the plurality of electrical contacts of a SIP device disposed in a corresponding one of the cells. The lest hive is operable to simultaneously, electrically test at least a predetermined number of the number of the SIP devices in each tray engaged by the hive without removing the SIP devices from the tray.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: Semiconductor Testing Advanced Research Lab Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Publication number: 20080252321Abstract: Apparatus for testing micro SD devices each having a plurality of electrical leads is described. The and apparatus utilizes industry standard JEDEC trays and tests all devices in such trays at the same time.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: Semiconductor Testing Advanced Research Lab Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Publication number: 20080252313Abstract: A method for testing System-In-Package (SIP) devices each having a plurality of electrical contacts is described. The method and apparatus utilizes industry standard JEDEC trays and tests at least a predetermined portion of all devices in such trays at the same time.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: Semiconductor Testing Advanced Research Lab Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Publication number: 20080252320Abstract: Apparatus for testing micro SD devices each having a plurality of electrical leads is described. The apparatus utilizes industry standard JEDEC trays and tests all devices in such trays at the same time. The apparatus comprises a test hive comprising: a plurality of test circuits corresponding in number to at least a predetermined number of cells in the tray: and a plurality of groups of test contacts, each group is coupled to one of the test circuits and is oriented to engage the plurality of electrical contacts of a micro SD device disposed in a corresponding one of the cells. The test hive is operable to simultaneously, electrically test at least a predetermined number of the number of the micro SD devices in each tray engaged by the hive without removing the micro SD devices that did pass electrical testing until a tray of electrically tested micro SD devices is fully populated with micro SD devices that did pass electrical testing.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: Semiconductor Testing Advanced Research Lab Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Publication number: 20080252322Abstract: A method for testing System-In-Package (SIP) devices such as micro SD devices each having a plurality of electrical leads is described. The method utilizes industry standard JEDEC trays and tests all devices in such trays at the same time.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: Semiconductor Testing Advanced Research Lab Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Publication number: 20080252312Abstract: Apparatus for testing System-In-Package (SIP) devices each having a plurality of electrical leads is described. The apparatus utilizes industry standard JEDEC trays and tests all devices in such trays at the same time. The apparatus of the illustrative embodiment comprises a test hive comprising: a plurality of test circuits corresponding in number to the number of cells in the tray; and a plurality of groups of test contacts, each of the groups of the test contacts being coupled to one of the test circuits and being oriented to engage the plurality of electrical contacts of a SIP device disposed in a corresponding one of the cells, the test hive being operable to simultaneously, electrically test all of the SIP devices in each tray engaged by the hive without removing the SIP devices from the tray.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: Semiconductor Testing Advanced Research Lab Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Publication number: 20080252317Abstract: Apparatus for testing System-In-Package (SIP) devices is described. The apparatus utilizes industry standard JEDEC trays and transports the trays into a tester.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: Semiconductor Testing Advanced Research Lab Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Publication number: 20080252319Abstract: Apparatus for testing System-In-Package (SIP) devices each having a plurality of electrical contacts is described. The apparatus utilizes industry standard JEDEC trays and tests at least a predetermined portion of the devices in such trays at the same time.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: Semiconductor Testing Advanced Research Lab Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Publication number: 20080252323Abstract: A method and apparatus for testing micro SD devices each having a plurality of electrical leads is described. The method and apparatus utilizes industry standard JEDEC trays and tests all devices in such trays at the same time.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: Semiconductor Testing Advanced Research Lab Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen
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Publication number: 20080252318Abstract: A method for testing micro SD devices each having a plurality of electrical leads is described. The method utilizes industry standard JEDEC trays and tests at least a predetermined portion of the devices in such trays at the same time.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: Semiconductor Testing Advanced Research Lab Inc.Inventors: James E. Hopkins, Michael Peter Costello, Herbert Tsai, Ching-Too Chen