Patents by Inventor Hermanus Leonardus Peek
Hermanus Leonardus Peek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10128190Abstract: The invention relates to a semiconductor device comprising: i) a substrate (1) comprising an insulating layer (2), wherein the electrically insulating layer (2) comprises a recess (99), and ii) a first conductive wire (20). The first conductive wire (20) comprises a first conductive sub-layer (22) provided within the recess (99), and comprises a second conductive sub-layer (24) provided on the first conductive sub-layer (22) forming a shunt for the first conductive sub-layer (22), wherein the first conductive sub-layer (22) comprises tungsten and the second conductive sub-layer (24) comprises aluminum, wherein the first conductive sub-layer (22) and the second conductive sub-layer (24) are substantially planar, and wherein the second conductive sub-layer (24) has substantially the same pattern as the first conductive sub-layer (22). The invention provides a semiconductor device, wherein the charge transport problem is improved, while ensuring a large packing density and a full flat-topology.Type: GrantFiled: April 23, 2012Date of Patent: November 13, 2018Assignee: TELEDYNE DALSA B.V.Inventors: Hermanus Leonardus Peek, Willem Hendrik Maes, Wilco Klaassens
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Publication number: 20150325519Abstract: The invention relates to a semiconductor device comprising: i) a substrate (1) comprising an insulating layer (2), wherein the electrically insulating layer (2) comprises a recess (99), and ii) a first conductive wire (20). The first conductive wire (20) comprises a first conductive sub-layer (22) provided within the recess (99), and comprises a second conductive sub-layer (24) provided on the first conductive sub-layer (22) forming a shunt for the first conductive sub-layer (22), wherein the first conductive sub-layer (22) comprises tungsten and the second conductive sub-layer (24) comprises aluminum, wherein the first conductive sub-layer (22) and the second conductive sub-layer (24) are substantially planar, and wherein the second conductive sub-layer (24) has substantially the same pattern as the first conductive sub-layer (22). The invention provides a semiconductor device, wherein the charge transport problem is improved, while ensuring a large packing density and a full flat-topology.Type: ApplicationFiled: April 23, 2012Publication date: November 12, 2015Applicant: Teledyne Dalsa B.V.Inventors: Hermanus Leonardus PEEK, Willem Hendrik MAES, Wilco KLAASSENS
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Patent number: 7525330Abstract: The semiconductor device (11) of the invention comprises a circuit covered by a passivation structure (50). It is provided with a first and a second security element (12A, 12B) which comprise local areas of the passivation structure (50), and with a first and a second electrode (14,15). The security elements (12A, 12B) have a first and a second impedance, respectively, which impedances differ. This is realized in that the passivation structure has an effective dielectric constant that varies laterally over the circuit. Actual values of the impedances are measured by measuring means and transferred to an access device by transferring means. The access device comprises or has access to a central database device for storing the impedances. The access device furthermore may compare the actual values with the stored values of the impedances in order to check the authenticity or the identity of the semiconductor device.Type: GrantFiled: November 28, 2002Date of Patent: April 28, 2009Assignee: NXP, B.V.Inventors: Petra Elisabeth De Jongh, Edwin Roks, Robertus Adrianus Maria Wolters, Hermanus Leonardus Peek
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Semiconductor device card methods of initializing checking the authenticity and the identity thereof
Patent number: 7309907Abstract: The semiconductor device (11) of the invention comprises a circuit that is covered by a passivation structure. It is provided with a first security element (12) that comprises a local area of the passivation structure and which has a first impedance. Preferably, a plurality of security elements (12) is present, whose the impedances differ. The semiconductor device (11) further comprises measuring means (4) for measuring an actual value of the first impedance, and a memory (7) comprising a first memory element (7A) for storing the actual value as a first reference value in the first memory element (7A). The semiconductor device (11) of the invention can be initialized by a method wherein the actual value is stored as the first reference value. Its authenticity can be checked by comparison of the actual value again measured and the first reference value.Type: GrantFiled: November 28, 2002Date of Patent: December 18, 2007Assignee: NXP B.V.Inventors: Petra Elisabeth De Jongh, Edwin Roks, Robertus Adrianus Maria Wolters, Hermanus Leonardus Peek -
Patent number: 6597024Abstract: A charge coupled device has a hydrogen diffusion path to diffuse hydrogen to a silicon surface. The hydrogen diffusion path extends through a top silicon oxide layer that itself extends through a first aperture in a top silicon nitride layer. The first aperture overlays a conductor formed of polycrystalline silicon at a location that transversely overlays a channel stop. The hydrogen diffusion path extends through the conductor and through an extension of the conductor that itself extends through a second aperture in a lower silicon nitride layer. The lower silicon nitride layer being one part of a gate dielectric film. The gate dielectric film also includes a lower silicon oxide layer disposed between the lower silicon nitride layer and the silicon surface. The hydrogen diffusion path extends through the lower silicon oxide layer to reach the silicon surface.Type: GrantFiled: October 2, 2001Date of Patent: July 22, 2003Assignee: Dalsa CorporationInventors: Hermanus Leonardus Peek, Joris Pieter Valentijn Maas, Daniel Wihelmus Elisabeth Verbugt
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Patent number: 6500691Abstract: The image sensor comprises a semiconductor body (1) having gate electrodes (3, 4) at a surface (2), each gate electrode being combined with the semiconductor body (1) and an intermediate dielectric (14) so as to form a MOS capacitor (5), which gate electrodes (3, 4) include a portion (6) which is thinner than a surrounding zone (7), a photosensitive region (8) in the semiconductor body (1) being situated below each gate electrode (3, 4), said photosensitive region (8) being capable of absorbing electromagnetic radiation and converting said radiation to electric charge. The MOS capacitors (5) are arranged next to each other so as to form an array (9), with the gate electrodes (3, 4) in a row (10) electrically contacting each other, and the gate electrodes (3, 4) in a column (11) being mutually separated only by electrically insulating material (12). The image sensor has an improved photosensitivity, particularly for electromagnetic radiation with a short wavelength.Type: GrantFiled: September 5, 2001Date of Patent: December 31, 2002Assignee: Koninklijke Philips ElectronicsInventors: Gregory Lee Kreider, Hermanus Leonardus Peek, Wilco Klaassens
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Publication number: 20020063786Abstract: A charge-coupled image sensor comprising a silicon body (1) wherein parallel channel regions (12), mutually separated by channel stop regions (16), are formed so as to be adjacent to a surface (2) of the body. The surface is provided with a gate dielectric (3, 4) composed of a silicon oxide layer (3) covered with a silicon nitride layer (4). Gate electrodes (18, 21, 33) of polycrystalline silicon are formed on the gate dielectric, which gate electrodes cross the channel regions and the channel stop regions. At least a number of the gate electrodes extend into diffusion holes (17), at the location where the gate electrodes and the channel stop regions intersect, which diffusion holes are formed in the silicon nitride layer of the gate dielectric. An insulating layer (24) of silicon oxide is formed on all gate electrodes, said insulating layer being provided with shunt electrodes (27) situated above the channel stop regions.Type: ApplicationFiled: October 2, 2001Publication date: May 30, 2002Inventors: Hermanus Leonardus Peek, Joris Pieter Valentijn Maas, Daniel Wilhelmus Elisabeth Verbugt
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Publication number: 20020056860Abstract: The image sensor comprises a semiconductor body (1) having gate electrodes (3, 4) at a surface (2), each gate electrode being combined with the semiconductor body (1) and an intermediate dielectric (14) so as to form a MOS capacitor (5), which gate electrodes (3, 4) include a portion (6) which is thinner than a surrounding zone (7), a photosensitive region (8) in the semiconductor body (1) being situated below each gate electrode (3, 4), said photosensitive region (8) being capable of absorbing electromagnetic radiation and converting said radiation to electric charge. The MOS capacitors (5) are arranged next to each other so as to form an array (9), with the gate electrodes (3, 4) in a row (10) electrically contacting each other, and the gate electrodes (3, 4) in a column (11) being mutually separated only by electrically insulating material (12). The image sensor has an improved photosensitivity, particularly for electromagnetic radiation with a short wavelength.Type: ApplicationFiled: September 5, 2001Publication date: May 16, 2002Inventors: Gregory Lee Kreider, Hermanus Leonardus Peek, Wilco Klaassens
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Publication number: 20020022296Abstract: A method of manufacturing a charge-coupled image sensor, wherein a silicon slice (1) is provided at its surface with semiconductor zones (8, 12, 16) formed by implantation of ions of dopants and subsequent heat treatments. The surface (2) is provided with a gate dielectric (3, 4) comprising a layer of silicon oxide (3) and a layer of silicon nitride (4) deposited on said layer of silicon oxide (3). A system of electrodes (17, 20) is formed on the gate dielectric layer (3, 4). In this method, the semiconductor zones (8, 12, 16) are not formed in the silicon slice (1) until after the gate dielectric layer (3, 4) has been formed, the ions being implanted through the gate dielectric layer (3, 4). An image sensor thus formed has a very small dark current, a very low fixed pattern noise, and images formed by means of the sensor are practically free of white spots.Type: ApplicationFiled: June 25, 2001Publication date: February 21, 2002Inventors: Hermanus Leonardus Peek, Daniel Wilhelmus Elisabeth Verbugt, Monique Johanna Beenhakkers
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Patent number: 4077112Abstract: The invention relates to a charge transfer device (C.T.D.) with polycrystalline silicon electrodes which are provided on a nitride layer. The nitride layer has apertures between the polyelectrodes. Electrodes of a second metallization layer, for example, of aluminium, are provided via said apertures. The charge storage capacities per surface unit (and with equal voltages) can be made equal by subjecting the device for a short period of time to an oxidation treatment prior to providing the Al electrodes so that the oxide layer in the apertures can become thicker than below the Si electrodes.Type: GrantFiled: December 10, 1976Date of Patent: March 7, 1978Assignee: U.S. Philips CorporationInventors: Matthias Johannes Joseph Theunissen, Roelof Pieter Kramer, Hermanus Leonardus Peek