Patents by Inventor Hervé Jaouen
Hervé Jaouen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10535552Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.Type: GrantFiled: February 9, 2018Date of Patent: January 14, 2020Assignee: STMicroelectronics SAInventors: Didier Dutartre, Herve Jaouen
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Publication number: 20180166318Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.Type: ApplicationFiled: February 9, 2018Publication date: June 14, 2018Applicant: STMicroelectronics SAInventors: Didier Dutartre, Herve Jaouen
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Patent number: 9929039Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.Type: GrantFiled: March 27, 2015Date of Patent: March 27, 2018Assignee: STMicroelectronics SAInventors: Didier Dutartre, Herve Jaouen
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Publication number: 20170103913Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.Type: ApplicationFiled: March 27, 2015Publication date: April 13, 2017Applicant: STMicroelectronics SAInventors: Didier Dutartre, Herve Jaouen
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Patent number: 7396736Abstract: A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.Type: GrantFiled: August 29, 2005Date of Patent: July 8, 2008Assignee: STMicroelectronics SAInventors: Hervé Jaouen, Thomas Skotnicki, Malgorzata Jurczak
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Publication number: 20060258066Abstract: An integrated electronic circuit comprises active components disposed on the surface of a substrate and connected by electrical connections disposed within a metallization level. A dielectric material situated between the surface of the substrate and the metallization level, or in the metallization level, has a locally higher value of dielectric permittivity so as to selectively increase a capacitance between certain portions of the active components or of the connections. An electrical state of the circuit in operation is then stabilized, thanks to a higher electrical charge carried by the portions of the active components or of the connections whose capacitance is enhanced. The circuit can be a static random access memory cell.Type: ApplicationFiled: April 20, 2006Publication date: November 16, 2006Applicant: STMicroelectronics SAInventors: Jean-Pierre Schoellkopf, Philippe Roche, Herve Jaouen
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Patent number: 7038285Abstract: A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.Type: GrantFiled: December 6, 2000Date of Patent: May 2, 2006Assignee: STMicroelectronics SAInventors: Hervé Jaouen, Thomas Skotnicki, Malgorzata Jurczak
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Patent number: 7029927Abstract: A method of repairing a defect in an integrated electronic circuit caused by an incorrect lithographic mask includes the formation of an electrical isolation between two conducting parts of the circuit. The electrical isolation is obtained by at least partly filling, with an electrically insulating material, a volume hollowed out beforehand which would otherwise, and incorrectly, form an electrical connection between the two conducting parts. To do this, a mask having an aperture revealing the hollowed out volume is formed on the circuit, and the mask used to direct the filling of the electrically insulating material and correction of the lithography defined defect.Type: GrantFiled: February 13, 2004Date of Patent: April 18, 2006Assignee: STMicroelectronics S.A.Inventors: Jean-Pierre Schoellkopf, Hervé Jaouen
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Patent number: 7029991Abstract: The invention concerns a method comprising: 1) a first phase including steps which consist in forming in the upper part of a first initial semiconductor substrate a first layer of insulating material above a sectional plane of said first substrate, contacting the first layer of insulating material with the insulating upper part of a second initial substrate, so as to form a single layer of insulating material, a break at the sectional plane, so as to obtain an intermediate semiconductor substrate on the single insulating material layer; then, 2) in a second phase which consists in forming in the intermediate semiconductor substrate an additional insulating material layer adjacent to the single insulating material and topped with an upper layer of a final semiconductor substrate.Type: GrantFiled: June 21, 2001Date of Patent: April 18, 2006Assignee: STMicroelectronics S.A.Inventors: Vincent Le Goascoz, Herve Jaouen
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Publication number: 20060001113Abstract: A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.Type: ApplicationFiled: August 29, 2005Publication date: January 5, 2006Applicant: STMicroelectronics SAInventors: Herve Jaouen, Thomas Skotnicki, Malgorzata Jurczak
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Patent number: 6897545Abstract: The transistor includes an emitter region 17 disposed in a first isolating well 11, 150 formed in a semiconductor bulk. An extrinsic collector region 16 is disposed in a second isolating well 3, 150 formed in the semiconductor bulk SB and separated laterally from the first well by a bulk separator area 20. An intrinsic collector region is situated in the bulk separator area 20 in contact with the extrinsic collector region. An intrinsic base region 100 is formed which is thinner laterally than vertically and in contact with the intrinsic collector region and in contact with the emitter region through bearing on a vertical flank of the first isolating well facing a vertical flank of the second isolating well. An extrinsic base region 60 is formed which is substantially perpendicular to the intrinsic base region in the top part of the bulk separator area, and contact terminals C, B, E respectively in contact with the extrinsic collector region, the extrinsic base region, and the emitter region.Type: GrantFiled: May 9, 2002Date of Patent: May 24, 2005Assignee: STMicroelectronics S.A.Inventors: Olivier Menut, Herve Jaouen
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Publication number: 20040217305Abstract: A method of repairing a defect in an integrated electronic circuit caused by an incorrect lithographic mask includes the formation of an electrical isolation between two conducting parts of the circuit. The electrical isolation is obtained by at least partly filling, with an electrically insulating material, a volume hollowed out beforehand which would otherwise, and incorrectly, form an electrical connection between the two conducting parts. To do this, a mask having an aperture revealing the hollowed out volume is formed on the circuit, and the mask used to direct the filling of the electrically insulating material and correction of the lithography defined defect.Type: ApplicationFiled: February 13, 2004Publication date: November 4, 2004Applicant: STMicroelectronics S.A.Inventors: Jean-Pierre Schoellkopf, Herve Jaouen
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Patent number: 6800514Abstract: A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first sidewall. The isolation block further includes a drain extension zone in the substrate under the isolation block, and a drain region in contact with the drain extension zone. The drain region is in the substrate but is not covered by the isolation block.Type: GrantFiled: June 27, 2002Date of Patent: October 5, 2004Assignee: STMicroelectronics SAInventors: Thierry Schwartzmann, Hervé Jaouen
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Patent number: 6756279Abstract: A method for manufacturing a contact between a semiconductor substrate and a doped polysilicon layer deposited on the substrate with an interposed insulating layer, wherein elements adapted to making the insulating layer permeable to the migration of dopants from the polysilicon layer to the substrate are implanted.Type: GrantFiled: July 30, 2002Date of Patent: June 29, 2004Assignee: STMicroelectronics S.A.Inventors: Olivier Menut, Hervé Jaouen, Guillaume Bouche
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Publication number: 20040029325Abstract: The invention concerns a method comprising: 1) a first phase including steps which consist in forming in the upper part of a first initial semiconductor substrate a first layer of insulating material above a sectional plane of said first substrate, contacting the first layer of insulating material with the insulating upper part of a second initial substrate, so as to form a single layer of insulating material, a break at the sectional plane, so as to obtain an intermediate semiconductor substrate on the single insulating material layer; then, 2) in a second phase which consists in forming in the intermediate semiconductor substrate an additional insulating material layer adjacent to the single insulating material and topped with an upper layer of a final semiconductor substrate.Type: ApplicationFiled: August 1, 2003Publication date: February 12, 2004Inventors: Vincent Le Goascoz, Herve Jaouen
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Patent number: 6673703Abstract: A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.Type: GrantFiled: June 13, 2002Date of Patent: January 6, 2004Assignee: STMicroelectronics S.A.Inventors: Olivier Menut, Herve Jaouen
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Patent number: 6670686Abstract: A transmitter or receiver includes several transducers formed opposite an aperture in a package. Each transducer includes a deformable semiconductor membrane that is capable of conducting current. The membrane is separated from a substrate zone by a cavity. This allows the membrane to deform due to the effect of an acoustic pressure or of a Lorenz force.Type: GrantFiled: September 16, 2002Date of Patent: December 30, 2003Assignee: STMicroelectronics SAInventors: Hervé Jaouen, Thomas Skotnicki, Malgorzata Jurczak
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Patent number: 6623993Abstract: A method of determining the time for polishing the surface of an integrated circuit wafer on a polishing machine. A sample wafer is fabricated to include at least one high plateau and at least one low plateau joined by a sudden transition. At least one initial profile is topographically scanned, and the surface of the sample wafer is polished at a particular polishing pressure for a particular polishing time. The final profile of the polished layer is topographically scanned in the corresponding area, and the initial and final topographical scans of the sample wafer are converted into Fourier series. The surface of the wafer to be polished is topographically scanned, and the topographic scan of the wafer to be polished is converted into a Fourier series. The time for polishing the wafer to be polished is calculated from the Fourier series and the average thickness to be removed.Type: GrantFiled: July 3, 2001Date of Patent: September 23, 2003Assignee: STMicroelectronics S.A.Inventors: Emmanuel Perrin, Herve Jaouen
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Patent number: 6593204Abstract: A method of fabricating, from a first semiconductor substrate having two parallel main surfaces, a system including an islet of a semiconductor material surrounded by an insulative material and resting on another insulative material includes forming a layer of a first insulative material, and forming on the top main surface of the first semiconductor substrate a thin semiconductor layer forming the islet of semiconductor material. The thin semiconductor layer can be selectively etched relative to the first semiconductor substrate. A layer of a second insulative material is formed on exposed surfaces of the islet of semiconductor material and the thin semiconductor layer. The method further includes removing the first semiconductor substrate.Type: GrantFiled: July 26, 2001Date of Patent: July 15, 2003Assignee: STMicroelectronics SAInventors: Hervé Jaouen, Vincent Le Goascoz
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Publication number: 20030076095Abstract: The present invention relates to a magnetic sensor which comprises a thin deformable membrane (3) made of a conductive material constituting a first plate of a capacitor and coursed by an electric current, a second capacitor plate consisting of a doped region of a semiconductor substrate (1), and a layer of a gaseous dielectric (6) separating the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current. In addition, the invention relates to a process for fabricating this magnetic sensor and to a device for measuring magnetic field.Type: ApplicationFiled: September 5, 2002Publication date: April 24, 2003Inventors: Herve Jaouen, Thomas Skotnicki, Malgorzata Jurczak