Patents by Inventor Herve Guegnaud

Herve Guegnaud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230082905
    Abstract: According to one aspect, an integrated circuit includes a power amplifier having a succession of at least two amplifier stages. The two amplifier stages include a first amplifier stage configured to receive a radio frequency signal as input and a last amplifier stage configured to deliver as an output of an amplified radio frequency signal. The power amplifier further includes a safety circuit with a control circuit configured to compare the amplified radio frequency signal voltage with a threshold voltage. The safety circuit further comprises a gain reduction circuit configured to reduce a bias voltage of an upstream amplifier stage of the last amplifier stage when the amplified radio frequency signal voltage is greater than the threshold voltage.
    Type: Application
    Filed: February 15, 2021
    Publication date: March 16, 2023
    Inventors: Herve Guegnaud, Stephanie Venec, Guillaume Blamon
  • Patent number: 7764093
    Abstract: A PLL comprises a PFD, a loop filter and a VCO, as well as a voltage shift capacitor coupling the PFD and the VCO. A voltage shift control circuit is placed in parallel with the voltage shift capacitor. This circuit comprises controlled charging means, which are designed to charge the voltage shift capacitor according to a channel control signal. It also comprises controlled pre-charging means which are designed to accelerate the charging of the voltage shift capacitor by the controlled charging means. It further comprises controlled biasing means, designed to ensure the bias of the input during the pre-charging of the voltage shift capacitor.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: July 27, 2010
    Assignee: EADS Telecom
    Inventors: Michel Robbe, Hervé Guegnaud
  • Patent number: 7675445
    Abstract: In order to convert a complex analog signal into a complex digital signal in an analog-digital conversion device having two channels, I and Q respectively, in quadrature, each comprising an input and an associated output, each output being fed back onto said associated input so as to form a first and a second feedback loops each comprising a digital-analog converter, the device comprising a complex filter with a first stage and a last stage, after sampling (508), a signal integration is performed in a first stage (501) of the filter without introducing any substantial delay. Then, an integration is performed in the last stage (502) of the filter. A substantial delay (507) is then introduced and the output signal of the last stage is converted into a digital signal over several bits. The digital signal is injected into the feedback loop (108) of said channel and the digital signal is converted into a feedback signal.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: March 9, 2010
    Assignee: Eads Secure Networks
    Inventors: Michel Robbe, Stéphane Doucet, Hervé Guegnaud
  • Publication number: 20090015452
    Abstract: In order to convert a complex analog signal into a complex digital signal in an analog-digital conversion device having two channels, I and Q respectively, in quadrature, each comprising an input and an associated output, each output being fed back onto said associated input so as to form a first and a second feedback loops each comprising a digital-analog converter, the device comprising a complex filter with a first stage and a last stage, after sampling (508), a signal integration is performed in a first stage (501) of the filter without introducing any substantial delay. Then, an integration is performed in the last stage (502) of the filter. A substantial delay (507) is then introduced and the output signal of the last stage is converted into a digital signal over several bits. The digital signal is injected into the feedback loop (108) of said channel and the digital signal is converted into a feedback signal.
    Type: Application
    Filed: September 19, 2005
    Publication date: January 15, 2009
    Applicant: Eads Secure Networks
    Inventors: Michel Robbe, Stephane Doucet, Herve Guegnaud
  • Publication number: 20070024378
    Abstract: A PLL structure comprises a PFD, a loop filter and a VCO, as well as a voltage shift capacitor (Ca) coupling the PFD and the VCO. A voltage shift control circuit (50) is placed in parallel with the voltage shift capacitor. This circuit comprises controlled charging means (51), which are designed to charge the voltage shift capacitor according to a channel control signal. It also comprises controlled pre-charging means (52) which are designed to accelerate the charging of the voltage shift capacitor by the controlled charging means. It further comprises controlled polarization means (53), designed to ensure the polarization of the input during the pre-charging of the voltage shift capacitor.
    Type: Application
    Filed: May 17, 2004
    Publication date: February 1, 2007
    Inventors: Michael Robbe, Herve Guegnaud
  • Patent number: 6943715
    Abstract: The invention concerns a passband Sigma-Delta analog-to-digital converter comprising a first resonator and a second order second resonator, preferably of second order, whereof the respective central frequencies enable a high SNR in a relatively wide frequency band, and a MASH Sigma-Delta analog-to-digital converter incorporating at least two such cascaded converters.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: September 13, 2005
    Assignee: EADS Telecom
    Inventors: Patrick Radja, Michel Robbe, Hervé Guegnaud
  • Publication number: 20040174285
    Abstract: The invention concerns a passband Sigma-Delta analog-to-digital converter comprising a first resonator (101) and a second order second resonator (102), preferably of second order, whereof the respective central frequencies are adjustable, so as to enable a high SNR in a relatively wide frequency band, and a MASH Sigma-Delta analog-to-digital converter incorporating at least two such cascaded converters.
    Type: Application
    Filed: December 12, 2003
    Publication date: September 9, 2004
    Inventors: Patrick Radja, Michel Robbe, Herve Guegnaud
  • Patent number: 5901349
    Abstract: The device forms first and second signals by mixing the input radio signal with two respective quadrature waves of frequency f.sub.O. An algebraic sum of these two signals is phase-shifted by .+-.45.degree. or .+-.135.degree. at an intermediate frequency f.sub.I. An output signal is formed by an algebraic sum between the phase-shifted signal and the first or second signal, in such a way that, at the intermediate frequency f.sub.I, the output signal has a phase representative of that possessed by the input radio signal at a communication frequency f.sub.C of the form f.sub.O -f.sub.I or f.sub.O +f.sub.I, with rejection of the phase of the input radio signal at the image frequency 2f.sub.O -f.sub.C.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: May 4, 1999
    Assignee: Matra Communication
    Inventors: Herve Guegnaud, Michel Robbe
  • Patent number: 5751188
    Abstract: In order to process an input signal exhibiting a frequency modulation about an intermediate frequency, the demodulator includes a first mixer for producing a first signal exhibiting the frequency modulation about a transposition frequency lower than the intermediate frequency; a switched-capacitor phase-shifter receiving the first signal so as to produce a second signal exhibiting, with respect to the first signal, a phase-shift varying substantially linearly with frequency about the transposition frequency; two substantially identical low-pass filters receiving the second signal and the first signal respectively; and a second mixer for mixing the signals produced by the first and second low-pass filters, in order to deliver a baseband output signal.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: May 12, 1998
    Assignee: Matra Communication
    Inventors: Herve Guegnaud, Michel Robbe