Patents by Inventor Heui Gyun Ahn

Heui Gyun Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10313620
    Abstract: The present invention relates to a technology with enables an image signal processor to output image data at a faster speed while using a memory having a smaller capacity. The image signal processor includes a pair of line memories for storing image data output from an analog-digital converter such that the image data alternates in units of horizontal lines, and outputting the stored image data in units of blocks according to a first-in-first-out method.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: June 4, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang Wook Ahn, Yong Woon Lee, Huy Chan Jung, Heui-Gyun Ahn
  • Patent number: 10165169
    Abstract: The present invention provides an image processing package comprising: an image sensor for receiving an image of a subject, which is incident from the outside, in the form of light and converting the image of the subject into an image signal; and an image signal processor for processing the image signal which is output from the image sensor and reproducing the image of the subject, wherein the image processing package has a structure in which the image sensor is vertically stacked on the image signal processor.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc.
    Inventors: Huy Chan Jung, Heui-Gyun Ahn, Sang Wook Ahn, Yong Woon Lee
  • Patent number: 9613881
    Abstract: A semiconductor device having improved heat-dissipation characteristics is capable effectively discharging heat that is generated inside the semiconductor device of a three-dimensional laminated structure, to the outside of the semiconductor device by utilizing an internal connector used during bonding.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: April 4, 2017
    Assignee: SK Hynix Inc.
    Inventors: Heui Gyun Ahn, Sang Wook Ahn, Yong Woon Lee, Huy Chan Jung, Sung Chun Jun
  • Patent number: 9543348
    Abstract: The present invention relates to a backlight image sensor chip having improved chip driving performance, in which a region other than a pad region, on which a conductive pad is formed, and a sensing region, on which an optical filter is formed, is used as a region for auxiliary driving so that additional functions such as auxiliary power supply, auxiliary signal transmission and auxiliary operation control can be performed, without additional process, in the backlight image sensor chip having a restricted area, thereby improving the chip driving performance.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: January 10, 2017
    Assignee: SILICONFILE TECHNOLOGIES INC.
    Inventors: Kyoung-Sik Park, Heui Gyun Ahn, Min-Suk Ko, Gab-Hwan Cho
  • Publication number: 20160373629
    Abstract: The present invention provides an image processing package comprising: an image sensor for receiving an image of a subject, which is incident from the outside, in the form of light and converting the image of the subject into an image signal; and an image signal processor for processing the image signal which is output from the image sensor and reproducing the image of the subject, wherein the image processing package has a structure in which the image sensor is vertically stacked on the image signal processor.
    Type: Application
    Filed: November 27, 2014
    Publication date: December 22, 2016
    Inventors: Huy Chan JUNG, Heui-Gyun AHN, Sang Wook AHN, Yong Woon LEE
  • Publication number: 20160372512
    Abstract: The present invention relates to a technology for simply performing a process of forming a pad on the rear surface of a via hole in a packing process in a process of forming a pad of a wafer. The present invention is characterized by a packing process in a process for manufacturing a wafer, the packing process comprising the steps of: attaching glass to the upper portion of a micro lens and then separating a handling wafer from an element wafer, thereby exposing metal layers formed on the element wafer to the outside; and forming pads for the metal layers.
    Type: Application
    Filed: April 30, 2014
    Publication date: December 22, 2016
    Inventor: Heui Gyun AHN
  • Patent number: 9478464
    Abstract: A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: October 25, 2016
    Assignee: SILICONFILE TECHNOLOGIES INC.
    Inventors: Heui Gyun Ahn, Sang Wook Ahn, Yong Woon Lee, Huy Chan Jung, Do Young Lee
  • Publication number: 20160301888
    Abstract: The present invention relates to a technology with enables an image signal processor to output image data at a faster speed while using a memory having a smaller capacity. The image signal processor includes a pair of line memories for storing image data output from an analog-digital converter such that the image data alternates in units of horizontal lines, and outputting the stored image data in units of blocks according to a first-in-first-out method.
    Type: Application
    Filed: November 11, 2014
    Publication date: October 13, 2016
    Applicant: Siliconfile Technologies Inc.
    Inventors: Sang Wook AHN, Yong Woon LEE, Huy Chan JUNG, Heui-Gyun AHN
  • Publication number: 20160267946
    Abstract: The present invention provides a stack memory device and a method for operating same. The stack memory device, according to the present invention, is provided with: a first memory chip in which first type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each first type memory cell; and a second memory chip in which second type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each second type memory cell, wherein first pads are connected to the dump lines of the first type memory cells and second pads are connected to the dump lines of the second type memory cells, the first pads and the second pads having one-to-one correspondence.
    Type: Application
    Filed: October 27, 2014
    Publication date: September 15, 2016
    Inventors: Sang Wook Ahn, Huy Chan Jung, Yong Woon Lee, Heui-Gyun Ahn, Do Young Lee
  • Publication number: 20160268373
    Abstract: A semiconductor apparatus having a heat dissipating function and electronic equipment comprising the same includes a front surface on which semiconductor devices constituting a circuit a circuit are formed; and a rear surface including a convexo-concave surface. Thus, the heat dissipation effect of the semiconductor apparatus can be maximized even without attaching a heat dissipation plate thereto.
    Type: Application
    Filed: October 2, 2014
    Publication date: September 15, 2016
    Inventors: Min Suk KO, Kyoung Sik PARK, Gab Hwan CHO, Heui Gyun AHN, Sang Wook AHN, Yong Woon LEE, Huy Chan JUNG
  • Patent number: 9406652
    Abstract: A semiconductor memory is formed by stacking a plurality of substrates and memory cells on each substrate are connected by data dump lines. A switch may intervene between the memory cell and the data dump line. When data of each substrate is dumped by the data dump line, a problem of decrease in a speed and an increase in power consumption due to a parasitic component can be minimized. Further, a core circuit including the memory cell may be disposed on one substrate and a peripheral circuit unit may be disposed on the remaining substrates.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: August 2, 2016
    Assignee: SILICONFILE TECHNOLOGIES INC.
    Inventors: Sang Wook Ahn, Huy Chan Jung, Yong Woon Lee, Do Young Lee, Heui-Gyun Ahn
  • Publication number: 20160204157
    Abstract: The present invention relates to a backlight image sensor chip having improved chip driving performance, in which a region other than a pad region, on which a conductive pad is formed, and a sensing region, on which an optical filter is formed, is used as a region for auxiliary driving so that additional functions such as auxiliary power supply, auxiliary signal transmission and auxiliary operation control can be performed, without additional process, in the backlight image sensor chip having a restricted area, thereby improving the chip driving performance.
    Type: Application
    Filed: August 12, 2014
    Publication date: July 14, 2016
    Applicant: Siliconfile Technologies Inc.
    Inventors: Kyoung-Sik PARK, Heui Gyun AHN, Min-Suk KO, Gab-Hwan CHO
  • Publication number: 20160163595
    Abstract: A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon.
    Type: Application
    Filed: April 30, 2014
    Publication date: June 9, 2016
    Inventors: Heui Gyun AHN, Sang Wook AHN, Yong Woon LEE, Huy Chan JUNG, Do Young LEE
  • Publication number: 20160086869
    Abstract: A semiconductor device having improved heat-dissipation characteristics is capable effectively discharging heat that is generated inside the semiconductor device of a three-dimensional laminated structure, to the outside of the semiconductor device by utilizing an internal connector used during bonding.
    Type: Application
    Filed: May 9, 2014
    Publication date: March 24, 2016
    Inventors: Heui Gyun AHN, Sang Wook AHN, Yong Woon LEE, Huy Chan JUNG, Sung Chun JUN
  • Publication number: 20150325618
    Abstract: The present invention relates to a CMOS image sensor including a color microlens, in which the color characteristics of a microlens are improved by replacing a microlens made of a transparent material with a material having characteristics similar to those of a color filter, and a manufacturing method thereof. In accordance with the CMOS image sensor including a color microlens and the manufacturing method thereof according to the present invention, color characteristics is improved. Since formation processes of a color filter and a microlens are performed at one time, additional processes for planarization and step difference adjustment are not necessary, so that an entire process is simplified. In the progress of light, since there is no interface between materials, reflection, refraction and the like are reduced, so that it is possible to increase light efficiency.
    Type: Application
    Filed: April 24, 2013
    Publication date: November 12, 2015
    Applicant: SiliconFile Technologies Inc.
    Inventors: Heui Gyun AHN, Jun Ho WON
  • Publication number: 20150155323
    Abstract: The present invention relates to a chip-stacked image sensor and to a method for manufacturing the same. More particularly, the present invention relates to a chip-stacked image sensor having a heterogeneous junction structure and to a method for manufacturing the same, in which a first semiconductor chip and a second semiconductor chip are manufactured using substrate materials suitable for the characteristics of sensors formed on each semiconductor substrate, and the semiconductor chips are stacked to form an image sensor. According to the chip-stacked image sensor having a heterogeneous junction structure and the method for manufacturing the same, the material for a first semiconductor substrate used in a first semiconductor chip and the material for a second semiconductor substrate used in a second semiconductor chip are different from each other, thus enabling characteristics of sensors formed on each semiconductor chip to be properly exhibited.
    Type: Application
    Filed: May 10, 2012
    Publication date: June 4, 2015
    Inventors: Heui Gyun Ahn, Jun Ho Won
  • Patent number: 8993411
    Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.
    Type: Grant
    Filed: February 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Siliconfile Technologies Inc.
    Inventors: Heui-Gyun Ahn, Se-Jung Oh, In-Gyun Jeon, Jun-Ho Won
  • Patent number: 8816459
    Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 26, 2014
    Assignee: Siliconfile Technologies Inc.
    Inventors: In-Gyun Jeon, Se-Jung Oh, Heui-Gyun Ahn, Jun-Ho Won
  • Patent number: 8421134
    Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: April 16, 2013
    Assignee: Siliconfile Technologies Inc.
    Inventors: In Gyun Jeon, Se Jung Oh, Heui Gyun Ahn, Jun Ho Won
  • Patent number: 8420429
    Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 16, 2013
    Assignee: Siliconfile Technologies Inc.
    Inventors: In Gyun Jeon, Se Jung Oh, Heui Gyun Ahn, Jun Ho Won