Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: A flash memory cell and a method for fabricating the same are provided. A first conductive film exposing a predetermined area of a semiconductor substrate is formed on the semiconductor substrate, and a tunnel oxide and a first interlevel dielectric film are formed on the surface of the semiconductor substrate exposed by the first conductive film and on the surface of the first conductive film, respectively. A floating gate covering the tunnel oxide and extending to the upper portion of the first conductive film in the vicinity of the tunnel oxide is formed as a second conductive film, and a second interlevel dielectric film is formed on the surface of the floating gate. A third conductive film electrically connected to the first conductive film in the vicinity of the floating gate is formed on a second interlevel dielectric film, thereby forming a control gate electrode comprised of the first conductive film and the third conductive film.

Abstract: A charge-coupled device (CCD) is provided having improved charge transfer efficiency. This CCD is a portion of an image sensor and manufactured by first laminating a first oxidation film and a first nitride film one after the other on a semiconductor substrate and then forming a plurality of first gate electrodes on the first nitride film at predetermined intervals apart. A second oxidation film is formed only on an upper surface and along side walls of each of the first gate electrodes. The first nitride film exposed between the first gate electrodes is removed and a second nitride film is formed on the exposed first oxidation film and the second oxidation film. A second gate electrode is then formed on the second nitride film between adjacent first gate electrodes. An image sensor is obtained in which leakage current density between the gate electrodes is reduced and the dielectric characteristic of a gate dielectric film is improved.

Abstract: A charge-coupled device (CCD) is provides having improved charge transfer efficiency. This CCD is a portion of an image sensor and manufactured by first laminating a first oxidation film and a first nitride film one after the other on a semiconductor substrate and then forming a plurality of first gate electrodes on the first nitride film at predetermined intervals apart. A second oxidation film is formed only on an upper surface and along side walls of each of the first gate electrodes. The first nitride film exposed between the first gate electrodes is removed and a second nitride film is formed on the exposed first oxidation film and the second oxidation film. A second gate electrode is then formed on the second nitride film between adjacent first gate electrodes. An image sensor is obtained in which leakage current density between the gate electrodes is reduced and the dielectric characteristic of a gate dielectric film is improved.