Patents by Inventor Heung-Soo Im
Heung-Soo Im has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7787300Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.Type: GrantFiled: November 14, 2008Date of Patent: August 31, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: June Lee, Oh-Suk Kwon, Heung-Soo Im
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Patent number: 7602644Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.Type: GrantFiled: April 11, 2007Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: June Lee, Oh-Suk Kwon, Heung-Soo Im
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Publication number: 20090067250Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.Type: ApplicationFiled: November 14, 2008Publication date: March 12, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: June LEE, Oh-Suk KWON, Heung-Soo IM
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Publication number: 20070189079Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.Type: ApplicationFiled: April 11, 2007Publication date: August 16, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: June LEE, Oh-Suk KWON, Heung-Soo IM
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Patent number: 7227785Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.Type: GrantFiled: November 21, 2005Date of Patent: June 5, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: June Lee, Oh-Suk Kwon, Heung-Soo Im
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Patent number: 7042770Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.Type: GrantFiled: December 9, 2002Date of Patent: May 9, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: June Lee, Oh-Suk Kwon, Heung-Soo Im
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Publication number: 20060083063Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.Type: ApplicationFiled: November 21, 2005Publication date: April 20, 2006Applicant: Samsung Electronics Co., Ltd.Inventors: June Lee, Oh-Suk Kwon, Heung-Soo Im
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Patent number: 6996014Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.Type: GrantFiled: June 14, 2005Date of Patent: February 7, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: June Lee, Oh-Suk Kwon, Heung-Soo Im
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Publication number: 20050232011Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.Type: ApplicationFiled: June 14, 2005Publication date: October 20, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: June Lee, Oh-Suk Kwon, Heung-Soo Im
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Patent number: 6889268Abstract: Embodiments of the invention provide a multi-chip system that includes a first and a second semiconductor memory device. The memory devices are mounted in a single package. The multi-chip system has a continuous burst read mode of operation, in which a read operation can be successively carried out without latency even though an address region moves from the first semiconductor memory device to the second memory device.Type: GrantFiled: February 28, 2003Date of Patent: May 3, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Hyuk Chae, Heung-Soo Im
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Patent number: 6724682Abstract: Disclosed is a nonvolatile semiconductor memory device having selective multiple-speed operation modes selected by simple options. The nonvolatile semiconductor memory device includes a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings, the cell string formed with floating gate memory cell transistors such that their control gates each are respectively connected to a plurality of word lines, and its drain-source channels are series connected to each other between a string select transistor and a ground select transistor. The memory device also includes a multiple-speed mode option part for generating a multiple-speed option signal, and an addressing circuit for selecting a page size and block size of the memory cell array different from one another in response to a state of the multiple-speed option signal.Type: GrantFiled: May 17, 2002Date of Patent: April 20, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: June Lee, Heung-Soo Im, Sun-Mi Choi
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Patent number: 6671204Abstract: A memory device has an array of memory cells to store data, and a Y-gating circuit to gate data stored in a group of the memory cells. A page buffer is coupled between the memory cell array and the Y-gating circuit. The page buffer includes a dual register corresponding to each memory cell of the group. The dual register includes a first register and an associated second register. The first and second registers are adapted to exchange data with each other, with cells of the memory cell array, and with the Y-gating circuit.Type: GrantFiled: December 7, 2001Date of Patent: December 30, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Heung-Soo Im
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Patent number: 6603684Abstract: A semiconductor memory device is provided, which includes a chip enable buffer and an address buffer. The chip enable buffer generates first and second control signals having opposite phases of logic, the first and second control signals enable and disable operations of the semiconductor memory device, respectively. The address buffer includes an input terminal, and a blocking terminal connected to the input terminal, the input terminal receiving an external address signal under control of the first control signal, and the blocking terminal generating an address signal in response to the second control signal. The address buffer further includes a shift detecting circuit connected to the blocking terminal for generating first and second short pulses by detecting shift of the address signal, wherein the pluses are used as signals for reading data of the semiconductor memory device.Type: GrantFiled: April 18, 2002Date of Patent: August 5, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Heung-Soo Im
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Publication number: 20030117856Abstract: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.Type: ApplicationFiled: December 9, 2002Publication date: June 26, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: June Lee, Oh-Suk Kwon, Heung-Soo Im
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Patent number: 6545910Abstract: Disclosed is a non-volatile semiconductor memory device provided therein.with a word line defect check circuit. The non-volatile semiconductor memory device includes: a memory cell array including a plurality of cell array blocks including a plurality of cell strings that consist of floating gate memory cell transistors that its drain-source channels are in series connected each other between string select transistors and ground select transistors and that its control gates are correspondingly connected to a plurality of word lines, and a word line short check circuit that inputs different levels of voltage to each of the plurality of word lines that is adjacent from one another during a predetermined charging time, and that generates a short sense signal that indicates whether short between adjacent word lines is occurred by checking voltage levels of the word lines that were supplied with a same level of voltage, after the charging time is lapsed by a predetermined time.Type: GrantFiled: October 18, 2001Date of Patent: April 8, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Seok Byeon, Heung-Soo Im, Young-Ho Lim
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Publication number: 20030016562Abstract: A memory device has an array of memory cells to store data, and a Y-gating circuit to gate data stored in a group of the memory cells. A page buffer is coupled between the memory cell array and the Y-gating circuit. The page buffer includes a dual register corresponding to each memory cell of the group. The dual register includes a first register and an associated second register. The first and second registers are adapted to exchange data with each other, with cells of the memory cell array, and with the Y-gating circuit.Type: ApplicationFiled: December 7, 2001Publication date: January 23, 2003Applicant: Samsung Electronics Co., Ltd.Inventor: Heung-Soo Im
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Publication number: 20020181315Abstract: Disclosed is a nonvolatile semiconductor memory device having selective multiple-speed operation modes selected by simple options. The nonvolatile semiconductor memory device includes a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings, the cell string formed with floating gate memory cell transistors such that their control gates each are respectively connected to a plurality of word lines, and its drain-source channels are series connected to each other between a string select transistor and a ground select transistor. The memory device also includes a multiple-speed mode option part for generating a multiple-speed option signal, and an addressing circuit for selecting a page size and block size of the memory cell array different from one another in response to a state of the multiple-speed option signal.Type: ApplicationFiled: May 17, 2002Publication date: December 5, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: June Lee, Heung-Soo Im, Sun-Mi Choi
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Publication number: 20020171437Abstract: A semiconductor memory device is provided, which includes a chip enable buffer and an address buffer. The chip enable buffer generates first and second control signals having opposite phases of logic, the first and second control signals enable and disable operations of the semiconductor memory device, respectively. The address buffer includes an input terminal, and a blocking terminal connected to the input terminal, the input terminal receiving an external address signal under control of the first control signal, and the blocking terminal generating an address signal in response to the second control signal. The address buffer further includes a shift detecting circuit connected to the blocking terminal for generating first and second short pulses by detecting shift of the address signal, wherein the pluses are used as signals for reading data of the semiconductor memory device.Type: ApplicationFiled: April 18, 2002Publication date: November 21, 2002Applicant: Samsung Electronics Co., Ltd.Inventor: Heung-Soo Im
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Publication number: 20020145907Abstract: Disclosed is a non-volatile semiconductor memory device provided therein with a word line defect check circuit.Type: ApplicationFiled: October 18, 2001Publication date: October 10, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Dae-Seok Byeon, Heung-Soo IM, Young-Ho Lim
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Patent number: 6433590Abstract: A sense amplifier circuit includes a first voltage-controlled current source to supply current proportional to a first bias voltage to a reference node and a second voltage-controlled current source to supply current proportional to a second bias voltage to a sensing node. The first and second bias voltages are internally generated in response to an externally applied sense amp control signal. A current mirror circuit is also provided for the sense amplifier circuit. The current mirror circuit commonly deliver current proportional to the voltage level of the reference node to the reference and sensing nodes. A differential amplifier amplifies a difference voltage between reference and sensing nodes.Type: GrantFiled: June 22, 2000Date of Patent: August 13, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Woo Lee, Heung-Soo Im