Patents by Inventor Heung Sup Chun

Heung Sup Chun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6043430
    Abstract: A bottom lead package is capable of increasing a memory capacity for a mounting position on a mother board by stacking several semiconductor packages such that exposed surfaces of leads on upper and lower surfaces of the package are aligned. The package includes a semiconductor chip, a plurality of lower leads attached to the lower side of the chip by an adhesive, a plurality of upper leads attached to the upper side of the chip by an adhesive and to the upper surfaces of the lower leads, wherein metal wires electrically connect the upper leads with a plurality of chip pads formed on the chip, and wherein a molding section packages the chip, the metal wires and the upper and lower leads, such that the upper and lower surfaces of the upper and lower leads, respectively, are externally exposed.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: March 28, 2000
    Assignee: LG Semicon Co., Ltd.
    Inventor: Heung-Sup Chun
  • Patent number: 5923080
    Abstract: A semiconductor apparatus having an insulation coating section at an outer section of an outer lead so as to reduce the number of inferior products at the time of bonding a fine pitch outer lead, which includes an insulation coating section formed at an outer portion of an outer lead of a TAB tape so as to prevent electric short between outer leads which occurs due to a conduction ball contained in ACA/ACF during a TAB outer lead bonding.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: July 13, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Heung Sup Chun
  • Patent number: 5849609
    Abstract: An improved semiconductor package includes an insulating film carrying conductive balls disposed between a substrate and a printed circuit board. The conductive balls mounted in the insulating film are precisely connected to lower surfaces of conductive patterns formed at the substrate and pads of the printed circuit board. A method for mounting the improved semiconductor package on the printed circuit board includes aligning a package having a plurality of exposed electrical connect terminals with upper surfaces of a plurality of conductive balls formed in an insulating film, aligning lower surfaces of the conductive balls with a plurality of pads formed on the printed circuit board, and electrically connecting the exposed electrical connect terminals, the ends of the conductive balls and the pads of the printed circuit board by a reflow process.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: December 15, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Heung Sup Chun
  • Patent number: 5731636
    Abstract: An improved semiconductor apparatus having conductive metallic protrusions formed on a bonding pad, thus improving an interconnection between a bonding pad and a bump formed on a substrate, which includes conductive metallic protrusions formed on said bonding pad of said substrate.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: March 24, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Heung Sup Chun
  • Patent number: 5644169
    Abstract: A mold and a method for manufacturing a semiconductor package and the semiconductor package manufactured thereby.The semiconductor package includes a chip attached to a paddle of a lead frame. And with electrically connecting the chip and inner leads of lead frame with a metal wire, a semi-finished product having electric connections is molded by using molding dies having an extrusion in a cavity for providing an opening on an upper portion of a light receiving region of the chip, and a transparent lid is provided on the upper portion of the opening of the semiconductor package.With the invention being able to provide an excellent resin semiconductor package and improved manufacturing processes, thereby reducing the manufacturing cost, enhancing a productivity and making a manufacturing process simpler.
    Type: Grant
    Filed: April 3, 1996
    Date of Patent: July 1, 1997
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Heung Sup Chun
  • Patent number: 5572068
    Abstract: A multi-chip semiconductor package and a method for manufacturing such a package. The package includes a plurality of inner leads of a lead frame, upper and lower semiconductor chips electrically connected to upper and lower surfaces of said inner leads, respectively. The upper and lower chips each has a plurality of pads each having a solder formed thereon. The solder is connected to each inner lead by a soldering, thereby causing the upper and lower chips to be electrically connected to the inner lead, respectively. The method includes the steps of forming polyimide layers on opposite sides of surfaces of the semiconductor chips, forming solders on pads of the semiconductor chips, upon locating inner leads with respect to the solders in order to be disposed at a direction, connecting the inner leads to the solders, and upon superposing an overturned chip on another chip, performing an encapsulation epoxy to the chips in order to cause the chips to be connected to each other.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: November 5, 1996
    Assignee: Goldstar Electron Co., Inc.
    Inventor: Heung Sup Chun