Abstract: A power conversion device includes a host device to control each submodule, and a plurality of repeating devices to relay communication between the host device and each submodule. The host device includes a command information generator to generate command information including an arm command, and a communication controller provided for each arm. Each of a plurality of communication controllers extracts, from the command information, an arm command associated with the communication controller, and transmits a communication frame including the extracted arm command to a repeating device that is connected to each submodule included in the arm associated with the communication controller.

Abstract: A page display system is provided for improving an intuitive visibility of letters and lines of letters as patterns by increasing the time for displaying each page. A formatter 13 of the page display system interprets and arrange the structured text 11 into page units, a rasterizer expands letters of the structured text 11 into fonts to form image patterns and generate each page image by synthesizing with images of attached data 12 and the like, and the image buffer 15 temporarily stores the thus produced page images. The image composer 16 acquires page images from the image buffer and composes a plurality of images upon necessity, the display device 17 displays page images. The page scroll controller 19 adjust the composition of images by the image composer 16. The timer 20 transmits information indicating the passage of time.

Abstract: A memory test pattern generator generates a memory test pattern by reading out data from a microinstruction program memory according to an instruction of an address counter and causing an address generator, a data generator and a timing generator to generate an address, data and a timing signal, respectively, according to the read-out data. To test a memory device, which has internal address generation means and is capable of address accessing by a clock signal, data representing the number of times of internal address is set in a repeat register. When a signal representing the internal address mode is read out from the microinstruction program memory, the increment of the address counter is stopped by a repeat controller, and the operation in the address and data generators is inhibited. At the same time, a timing set controller and an internal address generator are rendered operative, whereby an internal address is generated.