Abstract: A semiconductor device according to one embodiment of this invention includes: a semiconductor chip; a plurality of external connection pads and a plurality of first test pads, both of which are formed in a central region of a top surface of the semiconductor chip; a plurality of external connection electrodes each formed on a corresponding one of the external connection pads, the external connection electrodes being for connecting the external connection pads and an outside of the semiconductor device.

Abstract: A semiconductor device according to one embodiment of this invention includes: a semiconductor chip; a plurality of external connection pads and a plurality of first test pads, both of which are formed in a central region of a top surface of the semiconductor chip; a plurality of external connection electrodes each formed on a corresponding one of the external connection pads, the external connection electrodes being for connecting the external connection pads and an outside of the semiconductor device.

Abstract: A semiconductor integrated circuit device including a dummy via is disclosed. In the semiconductor integrated circuit device, problems such as reduction in the designability and increase in fabrication cost which result from the existence of a dummy wire connected to the dummy via are suppressed. The semiconductor integrated circuit device includes a substrate and three or more wiring layers formed on the substrate. The dummy via connects between a first wiring layer and a second wiring layer. The dummy wire connected to the dummy via exists in the second wiring layer. A protrusion amount of the dummy wire is smaller than a protrusion amount of an intermediate wire included in a stacked via structure.

Abstract: A semiconductor integrated circuit device including a dummy via is disclosed. In the semiconductor integrated circuit device, problems such as reduction in the designability and increase in fabrication cost which result from the existence of a dummy wire connected to the dummy via are suppressed. The semiconductor integrated circuit device includes a substrate and three or more wiring layers formed on the substrate. The dummy via connects between a first wiring layer and a second wiring layer. The dummy wire connected to the dummy via exists in the second wiring layer. A protrusion amount of the dummy wire is smaller than a protrusion amount of an intermediate wire included in a stacked via structure.

Abstract: A semiconductor apparatus according to the present invention comprises a semiconductor wafer, a plurality of semiconductor chips provided on the semiconductor wafer, a dicing lane provided between the adjacent two semiconductor chips and representing a region to be cut off when the semiconductor wafer is cut for each of the semiconductor chips and a plurality of probing pads disposed in a row on the dicing lane, and connecting parts for connecting the respective probing pads to one of the semiconductor chips facing each other with the probing pads interposed therebetween, wherein the semiconductor chips are connected to at least one of the plurality of probing pads via the connecting parts.

Abstract: A multifocal ocular lens having a vision correction area including at least one distant vision correction region having a first optical power value for distant vision correction and at least one near vision correction region having a second optical power value for near vision correction, wherein the vision correction area further includes a central intermediate-distance vision correction region which has a third optical power value for intermediate vision correction between the first and second optical power values and which is located in a central portion of the vision correction area such that the distant and near vision correction regions are located radially outwardly of the central intermediate-distance vision correction region.

Abstract: A multifocal ocular lens having a vision correction area which includes a central and outer vision correction region, an intermediate region located between the central and outer regions, and an intermediate-distance vision correction region located radially outwardly of and adjacent to the outer region, and which has an optical axis with which centers of these regions are aligned, the central and outer vision correction regions having respective different first and second optical power values, wherein the optical power of the intermediate region located between the central and outer regions is represented by a combination of two different quadratic curves connected to each other at a point of inflection which corresponds to a desired third optical power between the first and second values, and wherein the intermediate-distance vision correction region located radially outwardly of the outer region includes radially inner and outer varying-power zones, the optical power in the radially inner varying-power zon

Abstract: A toric multifocal lens including a plurality of vision correction regions having centers on a common optical center axis, the plurality of vision correction regions providing respective different values of a spherical optical power, each of the plurality of vision correction regions having an optical power for correction of astigmatism, wherein the improvement comprises: at least one of a cylindrical optical power and a cylindrical axis orientation which determine the optical power for correction of astigmatism being different in at least two different vision correction regions of the plurality of vision correction regions, so that the at least two different vision correction regions have respective different values of the optical power for correction of astigmatism.