Patents by Inventor Hideaki Teranishi
Hideaki Teranishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11257676Abstract: A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.Type: GrantFiled: June 28, 2018Date of Patent: February 22, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hideaki Matsuyama, Shinya Takashima, Katsunori Ueno, Ryo Tanaka, Masaharu Edo, Daisuke Mori, Hirotaka Suda, Hideaki Teranishi, Chizuru Inoue
-
Patent number: 11062907Abstract: A nitride semiconductor device is provide, the nitride semiconductor device including: an epitaxial layer; and an ion implantation layer that is provided on the epitaxial layer over a continuous depth range that extends over 100 nm or longer, and has a P type doping concentration equal to or higher than 1×1017 cm?3, wherein the ion implantation layer has a region with a crystal defect density equal to or lower than 1×1016 cm?3, the region being located in a range which is on an upper-surface-side of an interface between the epitaxial layer and the ion implantation layer, and is within 100 nm from the interface.Type: GrantFiled: March 12, 2019Date of Patent: July 13, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Shinya Takashima, Ryo Tanaka, Yuta Fukushima, Hideaki Teranishi
-
Publication number: 20190304788Abstract: A nitride semiconductor device is provide, the nitride semiconductor device including: an epitaxial layer; and an ion implantation layer that is provided on the epitaxial layer over a continuous depth range that extends over 100 nm or longer, and has a P type doping concentration equal to or higher than 1×1017 cm?3, wherein the ion implantation layer has a region with a crystal defect density equal to or lower than 1×1016 cm?3, the region being located in a range which is on an upper-surface-side of an interface between the epitaxial layer and the ion implantation layer, and is within 100 nm from the interface.Type: ApplicationFiled: March 12, 2019Publication date: October 3, 2019Inventors: Shinya TAKASHIMA, Ryo TANAKA, Yuta FUKUSHIMA, Hideaki TERANISHI
-
Publication number: 20190006184Abstract: A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.Type: ApplicationFiled: June 28, 2018Publication date: January 3, 2019Inventors: Hideaki MATSUYAMA, Shinya TAKASHIMA, Katsunori UENO, Ryo TANAKA, Masaharu EDO, Daisuke MORI, Hirotaka SUDA, Hideaki TERANISHI, Chizuru INOUE
-
Patent number: 10115587Abstract: A reverse blocking IGBT is manufactured using a silicon wafer sliced from a single crystal silicon ingot which is manufactured by a floating method using a single crystal silicon ingot manufactured by a Czochralski method as a raw material. A separation layer for ensuring a reverse blocking performance of the reverse blocking IGBT is formed by diffusing impurities implanted into the silicon wafer using a thermal diffusion process. The thermal diffusion process for forming the separation layer is performed in an inert gas atmosphere at a temperature equal to or more than 1290° C. and less than the melting point of silicon. In this way, no crystal defect occurs in the silicon wafer and it is possible to prevent the occurrence of a reverse breakdown voltage defect or a forward defect in the reverse blocking IGBT and thus improve the yield of a semiconductor element.Type: GrantFiled: February 23, 2012Date of Patent: October 30, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Haruo Nakazawa, Masaaki Ogino, Hidenao Kuribayashi, Hideaki Teranishi
-
Publication number: 20180308937Abstract: Provided is a MOS gate using a thermally oxidized film as a gate insulating film on the front surface of a silicon carbide substrate. A ratio of an excess carbon amount at an SiO2/SiC interface in relation to a carbon amount in the silicon carbide substrate is 0.1 or less. The excess carbon at the SiO2/SiC interface is generated during thermal oxidation for forming the gate insulating film. The excess carbon is a compound constituted of carbon atoms having the pi (it) bonds, and specifically is graphite, for example. The amount of nitrogen at the SiO2/SiC interface is 1.4×1015/cm2 to 1.8×1015/cm2, inclusive, for example.Type: ApplicationFiled: March 8, 2018Publication date: October 25, 2018Applicant: Fuji Electric Co., Ltd.Inventors: Takayuki HIROSE, Yutaka TERAO, Aki TAKIGAWA, Hideaki TERANISHI, Akira SAITO
-
Patent number: 9450070Abstract: A method for manufacturing a silicon semiconductor substrate including a diffusion layer prior to forming a semiconductor device thereon, includes providing a silicon semiconductor substrate which is manufactured by a floating zone method; and performing thermal diffusion at a heat treatment temperature that is equal to or higher than 1290° C. and that is lower than a melting temperature of a silicon crystal to form a diffusion layer with a depth of 50 ?m or more in the silicon semiconductor substrate, the thermal diffusion including a first heat treatment performed in an atmosphere consisting of oxygen or oxygen and at least one of argon, helium, or neon, followed by a second heat treatment performed in an atmosphere comprised of nitrogen or nitrogen and oxygen to form the diffusion layer. The method suppresses the occurrence of crystal defects, reduces the amount of inert gas used, and reduces manufacturing costs.Type: GrantFiled: October 10, 2014Date of Patent: September 20, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hideaki Teranishi, Haruo Nakazawa, Masaaki Ogino
-
Patent number: 9431270Abstract: A method for producing a semiconductor device is disclosed which includes a diffusion step of forming, on a CZ-FZ silicon semiconductor substrate, a deep diffusion layer involving a high-temperature and long-term thermal diffusion process which is performed at a thermal diffusion temperature of 1290° C. to a melting temperature of a silicon crystal for 100 hours or more; and a giving step of giving a diffusion source for an interstitial silicon atom to surface layers of two main surfaces of the silicon semiconductor substrate before the high-temperature, long-term thermal diffusion process. The step of giving the diffusion source for the interstitial silicon atom to the surface layers of the two main surfaces of the silicon semiconductor substrate is performed by forming thermally-oxidized films on two main surfaces of the silicon semiconductor substrate or by implanting silicon ions into surface layers of the two main surfaces of the silicon semiconductor substrate.Type: GrantFiled: September 5, 2014Date of Patent: August 30, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Haruo Nakazawa, Masaaki Ogino, Hidenao Kuribayashi, Hideaki Teranishi
-
Publication number: 20150031175Abstract: A method for manufacturing a semiconductor device, includes providing a silicon semiconductor substrate which is manufactured by a floating zone method; and performing thermal diffusion at a heat treatment temperature that is equal to or higher than 1290° C. and that is lower than a melting temperature of a silicon crystal to form a diffusion layer with a depth of 50 ?m or more in the silicon semiconductor substrate, the thermal diffusion including a first heat treatment performed in an oxygen atmosphere or a mixed gas atmosphere of oxygen and inert gas, and a second heat treatment performed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen to form the diffusion layer. The method suppresses the occurrence of crystal defects, reduces the amount of inert gas used, and reduces manufacturing costs.Type: ApplicationFiled: October 10, 2014Publication date: January 29, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hideaki TERANISHI, Haruo NAKAZAWA, Masaaki OGINO
-
Publication number: 20140377938Abstract: A method for producing a semiconductor device is disclosed which includes a diffusion step of forming, on a CZ-FZ silicon semiconductor substrate, a deep diffusion layer involving a high-temperature and long-term thermal diffusion process which is performed at a thermal diffusion temperature of 1290° C. to a melting temperature of a silicon crystal for 100 hours or more; and a giving step of giving a diffusion source for an interstitial silicon atom to surface layers of two main surfaces of the silicon semiconductor substrate before the high-temperature, long-term thermal diffusion process. The step of giving the diffusion source for the interstitial silicon atom to the surface layers of the two main surfaces of the silicon semiconductor substrate is performed by forming thermally-oxidized films on two main surfaces of the silicon semiconductor substrate or by implanting silicon ions into surface layers of the two main surfaces of the silicon semiconductor substrate.Type: ApplicationFiled: September 5, 2014Publication date: December 25, 2014Inventors: Haruo NAKAZAWA, Masaaki OGINO, Hidenao KURIBAYASHI, Hideaki TERANISHI
-
Patent number: 8809130Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.Type: GrantFiled: June 6, 2013Date of Patent: August 19, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Haruo Nakazawa, Motoyoshi Kubouchi, Hideaki Teranishi, Hideo Shimizu
-
Publication number: 20130344663Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.Type: ApplicationFiled: June 6, 2013Publication date: December 26, 2013Applicant: FUJI ELECTRIC CO., LTD.Inventors: Haruo NAKAZAWA, Motoyoshi Kubouchi, Hideaki Teranishi, Hideo Shimizu
-
Publication number: 20130260540Abstract: A reverse blocking IGBT is manufactured using a silicon wafer sliced from a single crystal silicon ingot which is manufactured by a floating method using a single crystal silicon ingot manufactured by a Czochralski method as a raw material. A separation layer for ensuring a reverse blocking performance of the reverse blocking IGBT is formed by diffusing impurities implanted into the silicon wafer using a thermal diffusion process. The thermal diffusion process for forming the separation layer is performed in an inert gas atmosphere at a temperature equal to or more than 1290° C. and less than the melting point of silicon. In this way, no crystal defect occurs in the silicon wafer and it is possible to prevent the occurrence of a reverse breakdown voltage defect or a forward defect in the reverse blocking IGBT and thus improve the yield of a semiconductor element.Type: ApplicationFiled: February 23, 2012Publication date: October 3, 2013Applicant: FUJI ELECTRIC CO., LTDInventors: Haruo Nakazawa, Masaaki Ogino, Hidenao Kuribayashi, Hideaki Teranishi
-
Patent number: 8460975Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.Type: GrantFiled: February 10, 2011Date of Patent: June 11, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Haruo Nakazawa, Motoyoshi Kubouchi, Hideaki Teranishi, Hideo Shimizu
-
Publication number: 20110207267Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.Type: ApplicationFiled: February 10, 2011Publication date: August 25, 2011Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventors: Haruo NAKAZAWA, Motoyoshi Kubouchi, Hideaki Teranishi, Hideo Shimizu
-
Patent number: 7476942Abstract: The SOI lateral semiconductor device includes a semiconductor region of a first conductivity type, a buried oxide film layer in the semiconductor region, a thin active layer on the buried oxide film layer, an anode region in the thin active layer, and a drain layer contacting the buried oxide film layer for confining the minority carriers injected from the anode region to the thin active layer within the thin active layer and for forming a structure that sustains a high breakdown voltage. The SOI lateral semiconductor device can provide a high breakdown voltage and low switching losses using the thin buried oxide film, which can be formed by an implanted oxygen (SIMOX) method.Type: GrantFiled: April 8, 2007Date of Patent: January 13, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Yasumasa Watanabe, Hideaki Teranishi, Naoto Fujishima
-
Publication number: 20070235804Abstract: The SOI lateral semiconductor device includes a semiconductor region of a first conductivity type, a buried oxide film layer in the semiconductor region, a thin active layer on the buried oxide film layer, an anode region in the thin active layer, and a drain layer contacting the buried oxide film layer for confining the minority carriers injected from the anode region to the thin active layer within the thin active layer and for forming a structure that sustains a high breakdown voltage. The SOI lateral semiconductor device can provide a high breakdown voltage and low switching losses using the thin buried oxide film, which can be formed by an implanted oxygen (SIMOX) method.Type: ApplicationFiled: April 8, 2007Publication date: October 11, 2007Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Yasumasa Watanabe, Hideaki Teranishi, Naoto Fujishima