Patents by Inventor Hideaki Yoshimi
Hideaki Yoshimi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11728424Abstract: According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area.Type: GrantFiled: October 26, 2020Date of Patent: August 15, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi Noma, Yusheng Lin, Kazuo Okada, Hideaki Yoshimi, Shunsuke Yasuda
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Publication number: 20220131002Abstract: According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area.Type: ApplicationFiled: October 26, 2020Publication date: April 28, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi NOMA, Yusheng LIN, Kazuo OKADA, Hideaki YOSHIMI, Shunsuke YASUDA
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Patent number: 11114402Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.Type: GrantFiled: February 23, 2018Date of Patent: September 7, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Takashi Noma, Kazuo Okada, Hideaki Yoshimi, Naoyuki Yomoda, Yusheng Lin
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Publication number: 20210272920Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.Type: ApplicationFiled: May 14, 2021Publication date: September 2, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Takashi NOMA, Kazuo OKADA, Hideaki YOSHIMI, Naoyuki YOMODA, Yusheng LIN
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Publication number: 20190267344Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.Type: ApplicationFiled: February 23, 2018Publication date: August 29, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Takashi NOMA, Kazuo OKADA, Hideaki YOSHIMI, Naoyuki YOMODA, Yusheng LIN
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Patent number: 9917010Abstract: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 ?m to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 ?m. As a result, a thickness of the entire semiconductor device can be reduced.Type: GrantFiled: April 8, 2014Date of Patent: March 13, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hideaki Yoshimi, Mitsuo Umemoto, Kazumi Onda, Kazumi Horinaka
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Patent number: 8809076Abstract: The invention provides a semiconductor device and a method of automatically inspecting the appearance, which achieves proper recognition of the size of a chipping occurring from an end portion of the semiconductor device toward the element forming region by an automatic appearance inspection machine, and prevents a problem of judging an appearance non-defective product as an appearance defective product. A semiconductor device includes a resin layer extending from an element forming region over a guard ring surrounding the element forming region so as to cover these except a plurality of portions of the guard ring, and a chipping extending from a chip end portion of a semiconductor device toward the end portion of the resin layer.Type: GrantFiled: January 25, 2013Date of Patent: August 19, 2014Assignee: Semiconductor Components Industries, LLCInventors: Hideaki Yoshimi, Shinzo Ishibe, Eiji Kurose
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Publication number: 20140220739Abstract: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 ?m to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 ?m. As a result, a thickness of the entire semiconductor device can be reduced.Type: ApplicationFiled: April 8, 2014Publication date: August 7, 2014Applicant: Semiconductor Components Industries, LLC.Inventors: Hideaki Yoshimi, Mitsuo Umemoto, Kazumi Onda, Kazumi Horinaka
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Patent number: 8736047Abstract: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 ?m to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 ?m. As a result, a thickness of the entire semiconductor device can be reduced.Type: GrantFiled: March 28, 2007Date of Patent: May 27, 2014Assignee: Semiconductor Components Industries, LLCInventors: Hideaki Yoshimi, Mitsuo Umemoto, Kazumi Onda, Kazumi Horinaka
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Patent number: 8648452Abstract: This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame.Type: GrantFiled: July 5, 2011Date of Patent: February 11, 2014Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Kiyoshi Saito, Yuji Umetani, Hideaki Yoshimi
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Publication number: 20140027894Abstract: This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame.Type: ApplicationFiled: September 27, 2013Publication date: January 30, 2014Applicants: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, SANYO SEMICONDUCTOR CO., LTD.Inventors: Kiyoshi SAITO, Yuji UMETANI, Hideaki YOSHIMI
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Publication number: 20130192078Abstract: The invention provides a semiconductor device and a method of automatically inspecting the appearance, which achieves proper recognition of the size of a chipping occurring from an end portion of the semiconductor device toward the element forming region by an automatic appearance inspection machine, and prevents a problem of judging an appearance non-defective product as an appearance defective product. A semiconductor device includes a resin layer extending from an element forming region over a guard ring surrounding the element forming region so as to cover these except a plurality of portions of the guard ring, and a chipping extending from a chip end portion of a semiconductor device toward the end portion of the resin layer.Type: ApplicationFiled: January 25, 2013Publication date: August 1, 2013Inventors: Hideaki YOSHIMI, Shinzo ISHIBE, Eiji KUROSE
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Publication number: 20110260311Abstract: This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame.Type: ApplicationFiled: July 5, 2011Publication date: October 27, 2011Applicants: SANYO Electric Co., Ltd.Inventors: Kiyoshi SAITO, Yuji Umetani, Hideaki Yoshimi
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Patent number: 7998794Abstract: This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame.Type: GrantFiled: August 12, 2009Date of Patent: August 16, 2011Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Kiyoshi Saito, Yuji Umetani, Hideaki Yoshimi
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Publication number: 20100052138Abstract: This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame.Type: ApplicationFiled: August 12, 2009Publication date: March 4, 2010Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Kiyoshi Saito, Yuji Umetani, Hideaki Yoshimi
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Publication number: 20070228554Abstract: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 ?m to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 ?m. As a result, a thickness of the entire semiconductor device can be reduced.Type: ApplicationFiled: March 28, 2007Publication date: October 4, 2007Applicant: Sanyo Electric Co., Ltd.Inventors: Hideaki Yoshimi, Mitsuo Umemoto, Kazumi Onda, Kazumi Horinaka