Abstract: A display device includes a temperature sensor which is arranged in the inside of a housing, and a control unit which calculates a temperature of a display panel based on an output value of the temperature sensor. The control unit calculates the temperature of the display panel based on a current output value of the temperature sensor and an output value of the temperature sensor received prior to the receiving of the current output value. With such a display device, the temperature of the display panel can be calculated with high accuracy even when a temperature of a device which constitutes a heat source is changed.

Abstract: On a liquid crystal panel, plural areas whose number is larger than that of temperature sensors are defined. In a memory, temperature relation information representing a relation between an output value of a temperature sensor and a temperature of each of the plural areas is stored. A controller acquires the output value of the temperature sensor and estimates, based on the temperature relation information and the acquired output value, the temperature of each of the plural areas. According to this configuration, the temperature of each of the plural areas defined on the liquid crystal panel can be obtained with a small number of temperature sensors.

Abstract: On a liquid crystal panel, plural areas whose number is larger than that of temperature sensors are defined. In a memory, temperature relation information representing a relation between an output value of a temperature sensor and a temperature of each of the plural areas is stored. A controller acquires the output value of the temperature sensor and estimates, based on the temperature relation information and the acquired output value, the temperature of each of the plural areas. According to this configuration, the temperature of each of the plural areas defined on the liquid crystal panel can be obtained with a small number of temperature sensors.

Abstract: A disk reproducing device comprising: clock signal extracting means for extracting a regenerative clock signal from a reproduced signal; synchronization detecting means for detecting a synchronizing signal from the reproduced signal; extracted clock signal verification means for verifying that the regenerative clock signal is correctly extracted; signal processing means for performing variable linear velocity reproduction; target reproducing speed setting means for setting a target reproducing speed; reproducing speed verification means for verifying that a reproducing speed reaches the target reproducing speed; and signal processing start command generating means for outputting a signal processing start command referring outputs of said extracted clock signal verification means and said reproducing speed verification means.

Abstract: A disk reproducing device comprising: clock signal extracting means for extracting a regenerative clock signal from a reproduced signal; synchronization detecting means for detecting a synchronizing signal from the reproduced signal; extracted clock signal verification means for verifying that the regenerative clock signal is correctly extracted; signal processing means for performing variable linear velocity reproduction; target reproducing speed setting means for setting a target reproducing speed; reproducing speed verification means for verifying that a reproducing speed reaches the target reproducing speed; and signal processing start command generating means for outputting a signal processing start command referring outputs of said extracted clock signal verification means and said reproducing speed verification means.

Abstract: A disk reproducing device comprising: clock signal extracting means for extracting a regenerative clock signal from a reproduced signal; synchronization detecting means for detecting a synchronizing signal from the reproduced signal; extracted clock signal verification means for verifying that the regenerative clock signal is correctly extracted; signal processing means for performing variable linear velocity reproduction; target reproducing speed setting means for setting a target reproducing speed; reproducing speed verification means for verifying that a reproducing speed reaches the target reproducing speed; and signal processing start command generating means for outputting a signal processing start command referring outputs of said extracted clock signal verification means and said reproducing speed verification means.

Abstract: A virtual RAM read address generating circuit (41) generates a virtual address on the basis of an output signal of a crystal oscillation circuit (36). A phase comparison circuit (39) which performs phase comparison with a write address, and a spindle control circuit (3) which controls rotation of a disk with reference to outputs of a frequency comparison circuit (38) and the phase comparison circuit (39) are disposed. Therefore, a phase error can be fed back to a spindle motor, thereby preventing linear velocity deviation from occurring in a steady state. By using the thus configured reproducing device, the reproduction quality in the case where a disk wherein recording was performed by the CLV system is reproduced by the variable linear velocity reproduction system is ensured, and both high-speed access and low power consumption are realized.

Abstract: A disk reproducing device comprising: clock signal extracting means for extracting a regenerative clock signal from a reproduced signal; synchronization detecting means for detecting a synchronizing signal from the reproduced signal; extracted clock signal verification means for verifying that the regenerative clock signal is correctly extracted; signal processing means for performing variable linear velocity reproduction; target reproducing speed setting means for setting a target reproducing speed; reproducing speed verification means for verifying that a reproducing speed reaches the target reproducing speed; and signal processing start command generating means for outputting a signal processing start command referring outputs of said extracted clock signal verification means and said reproducing speed verification means.

Abstract: A virtual RAM read address generating circuit (41) generates a virtual address-on the basis of an output signal of a crystal oscillation circuit (36). A phase comparison circuit (39) which performs phase comparison with a write address, and a spindle control circuit (3) which controls rotation of a disk with reference to outputs of a frequency comparison circuit (38) and the phase comparison circuit (39) are disposed. Therefore, a phase error can be fed back to a spindle motor, thereby preventing linear velocity deviation from occurring in a steady state. By using the thus configured reproducing device, the reproduction quality in the case where a disk wherein recording was performed by the CLV system is reproduced by the variable linear velocity reproduction system is ensured, and both high-speed access and low power consumption are realized.

Abstract: A virtual RAM read address generating circuit (41) generates a virtual address on the basis of an output signal of a crystal oscillation circuit (36). A phase comparison circuit (39) which performs phase comparison with a write address, and a spindle control circuit (3) which controls rotation of a disk with reference to outputs of a frequency comparison circuit (38) and the phase comparison circuit (39) are disposed. Therefore, a phase error can be fed back to a spindle motor, thereby preventing linear velocity deviation from occurring in a steady state. By using the thus configured reproducing device, the reproduction quality in the case where a disk wherein recording was performed by the CLV system is reproduced by the variable linear velocity reproduction system is ensured, and both high-speed access and low power consumption are realized.

Abstract: The invention is directed at ensuring stable track accessing despite the presence of backlash in a pickup drive mechanism, and at providing a precise track accessing operation not affected by the relative position or relative speed between pickup and carriage at the time a track access start instruction is issued. To achieve this, when the track access start instruction is issued in a tracking condition in which the pickup is following a track on a recording medium, the carriage is caused to begin to move in a track access direction by the action of a coarse actuator, while the pickup is still kept on track of the recording medium by means of a fine actuator.