Abstract: A constant voltage source supplies a bias current to a wireless receiver circuit. A bias current detector circuit detects the bias current, and outputs a detection result to a current controller circuit. The current controller circuit outputs the detection result of the bias current to a memory circuit. The current controller circuit controls the bias current detector circuit to stop operating thereof, and then controls the bias current to decrease when the detected bias current is larger than a predetermined first threshold value and controls the bias current to increase when the detected bias current is smaller than a second threshold value smaller than the first threshold value, based on the detection result stored in the memory circuit.

Abstract: A receiver circuit includes a low noise amplifier (LNA) 1 to which a received signal is input, a mixer 2 for mixing an output of the LNA and a local signal, a first low-pass filter 3 for receiving an output of the mixer, and a composite amplifier in which a fixed gain amplifier 4, a high-pass filter 5, and a gain control amplifier 6 are connected in this order from the input side. An output of the first low-pass filter is input to the fixed gain amplifier. The gain of the fixed gain amplifier is 0 dB or more. The maximum gain of the gain control amplifier is 0 dB or less. The receiver circuit can suppress a transient response due to DC voltage fluctuations, even if the gains are changed while signals are received in a communication mode that performs continuous reception.

Abstract: A communication control circuit includes a shift register and a control data selector, and controls controlled units according to a data signal, a clock signal and a strobe signal inputted via three serial signal lines. The shift register serial-to-parallel converts the data signal sequentially taken in according to the clock signal into a converted signal, and outputs the converted signal. The control data selector selects control data for controlling the corresponding controlled unit from the signal from the shift register, in response to a device definition signal for identifying the communication control circuit, and outputs the same control data.

Abstract: An object of the invention is to provide a receiving circuit where the quality of reception can be prevented from deteriorating when the gain changes, so that the good quality of the received signal can be preserved, as well as a receiving apparatus and a transmitting/receiving apparatus using the receiving circuit. In the configuration of the invention, a switch (113) is converted to a short state in response to a change in the gain of a variable gain amplifier (107) by means of a gain control apparatus 112, and thereby, the output terminal of a high pass filter (111) is fixed at a reference voltage and the cutoff frequency of a low pass filter (108) is increased. As a result, the period during which the DC voltage has transient response properties in the low pass filter (108) can be shortened, and this transient response prevented from passing through the high pass filter (111).

Abstract: A filtering apparatus includes a main filter, a variation detection circuit, and a variation correction circuit. The variation detection circuit includes a reference filter having at least one resistor and at least one capacitor, detects a variation of CR-product based on the resistor and the capacitor of the reference filter in response to each of a plurality of reference signals having different frequencies from each other, and then outputs a variation detection signal indicating a detected result. The variation correction circuit corrects frequency characteristics of the main filter on the basis of the variation detection signal.

Abstract: The direct conversion receiving apparatus has a gain control amplifier for variably amplifying a base band signal based on a gain switching control signal. A high pass filter has a first circuit including capacitors connected in parallel that are inserted in a path connecting an input terminal to an output terminal and switching effective total capacitance of the capacitors based on a first time constant switching control signal, and a second circuit including a resistor for providing a predetermined direct current voltage to the output terminal and switching the effective resistance value of the resistor based on a second time constant switching control signal. A control circuit outputs the gain switching control signal, and the first and second time constant switching control signals according to the change of the gain control of said gain control amplifier.

Abstract: A constant voltage source supplies a bias current to a wireless receiver circuit. A bias current detector circuit detects the bias current, and outputs a detection result to a current controller circuit. The current controller circuit outputs the detection result of the bias current to a memory circuit. The current controller circuit controls the bias current detector circuit to stop operating thereof, and then controls the bias current to decrease when the detected bias current is larger than a predetermined first threshold value and controls the bias current to increase when the detected bias current is smaller than a second threshold value smaller than the first threshold value, based on the detection result stored in the memory circuit.

Abstract: A filtering apparatus includes a main filter, a variation detection circuit, and a variation correction circuit. The variation detection circuit includes a reference filter having at least one resistor and at least one capacitor, detects a variation of CR-product based on the resistor and the capacitor of the reference filter in response to each of a plurality of reference signals having different frequencies from each other, and then outputs a variation detection signal indicating a detected result. The variation correction circuit corrects frequency characteristics of the main filter on the basis of the variation detection signal.

Abstract: Interruption of a reception signal is achieved by placing a first low noise amplifier into the sleep state, and short-circuiting a shunt switch provided between differential input terminals of a second low noise amplifier during a DC offset canceling period. Further, an antenna switch is switched to a circuit system where DC offset canceling is not performed for preventing the input of the reception signal to a circuit system where DC offset canceling is performed.

Abstract: An object of the invention is to provide a receiving circuit where the quality of reception can be prevented from deteriorating when the gain changes, so that the good quality of the received signal can be preserved, as well as a receiving apparatus and a transmitting/receiving apparatus using the receiving circuit. In the configuration of the invention, a switch (113) is converted to a short state in response to a change in the gain of a variable gain amplifier (107) by means of a gain control apparatus 112, and thereby, the output terminal of a high pass filter (111) is fixed at a reference voltage and the cutoff frequency of a low pass filter (108) is increased. As a result, the period during which the DC voltage has transient response properties in the low pass filter (108) can be shortened, and this transient response prevented from passing through the high pass filter (111).

Abstract: A receiver circuit includes a low noise amplifier (LNA) 1 to which a received signal is input, a mixer 2 for mixing an output of the LNA and a local signal, a first low-pass filter 3 for receiving an output of the mixer, and a composite amplifier in which a fixed gain amplifier 4, a high-pass filter 5, and a gain control amplifier 6 are connected in this order from the input side. An output of the first low-pass filter is input to the fixed gain amplifier. The gain of the fixed gain amplifier is 0 dB or more. The maximum gain of the gain control amplifier is 0 dB or less. The receiver circuit can suppress a transient response due to DC voltage fluctuations, even if the gains are changed while signals are received in a communication mode that performs continuous reception.

Abstract: The direct conversion receiving apparatus has a gain control amplifier for variably amplifying a base band signal based on a gain switching control signal. A high pass filter has a first circuit including capacitors connected in parallel that are inserted in a path connecting an input terminal to an output terminal and switching effective total capacitance of the capacitors based on a first time constant switching control signal, and a second circuit including a resistor for providing a predetermined direct current voltage to the output terminal and switching the effective resistance value of the resistor based on a second time constant switching control signal. A control circuit outputs the gain switching control signal, and the first and second time constant switching control signals according to the change of the gain control of said gain control amplifier.

Abstract: A filter device is provided that can easily achieve reduction in current consumption and whose variations can be corrected. A phase difference of a reference filter is detected by a phase difference detector, a control signal for correcting variations that is obtained as a result of the detection is held in a register, and a cut-off frequency of a main filter is selected according to the control signal thus held. Thus, once variations are detected, the reference filter and the phase difference detector that are used for detection of variations become no longer necessary and their operations can be halted, thereby achieving reduction in current consumption.

Abstract: Interruption of a reception signal is achieved by placing a first low noise amplifier into the sleep state, and short-circuiting a shunt switch provided between differential input terminals of a second low noise amplifier during a DC offset canceling period. Further, an antenna switch is switched to a circuit system where DC offset canceling is not performed for preventing the input of the reception signal to a circuit system where DC offset canceling is performed.

Abstract: Fixed pattern noise of an analog memory is reduced. Transfer paths of an address selection signal (SL) between an address generation unit (10) and respective storage elements (21) for storing an analog signal are constructed to have a substantially uniform electric characteristic in driving the storage elements (21) by the address selection signal (SL) to such an extent that the output signal of the analog memory is free from fixed pattern noise. A buffer unit (50) for temporarily storing and outputting the address selection signal is provided between the address generation unit (10) and the respective storage elements (21), and the buffer unit (50) is constructed to have an output characteristic substantially uniform between the storage elements (21). Also, lines between the buffer unit (50) and the storage elements (21) are constructed to have substantially the same electric characteristic.

Abstract: A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated.

Abstract: A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated.

Abstract: A comb filter easily implementable as a monolithic LSI without using a large-capacitance capacitor is provided. A comb-like frequency characteristic is realized by two delay circuits for delaying a signal for mutually different amounts of time and an operation circuit for deriving a sum or difference of the outputs thereof. An input select switch selectively outputs, instead of an image signal, a test signal, which is a DC signal having a predetermined amplitude, during a blanking interval of the image signal. A detector controls the gain of a variable-gain amplifier, provided for the output of either one of the delay circuits, in accordance with a difference between the output signal of the comb filter in response to the test signal and a predetermined reference signal. That is to say, the gain of the comb filter is controlled by using a stable test signal as a control signal, instead of a burst signal contained in an unstable image signal.

Abstract: The invention provides an analog FIFO memory from which a written analog signal can be accurately read by eliminating errors in the analog signal between the write operation and the read operation. Prior to the read operation for reading the analog signal from a memory cell through a memory bus, a reset operation for setting the memory bus at a predetermined potential is conducted so as to remove a charge stored in a parasitic capacitance of the memory bus. The input terminal of a read circuit is set at a predetermined potential, with a write circuit disconnected from the memory bus by using an input circuit and with the read circuit connected with the memory bus by using an output circuit. In this manner, the memory bus is set at the predetermined potential, and the charge stored in the parasitic capacitance is discharged. At this point, a switch in each memory cell is in an off-state, and hence, a charge corresponding to the analog signal can be retained in the memory cell.