Patents by Inventor Hidehisa Sakai
Hidehisa Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10575392Abstract: A cooling system includes a heat exchanger provided on a heat generating component, the heat exchanger having a size larger than the heat generating component, a leaf spring to extend from a first side of an upper surface of the heat exchanger to a second side opposite to the first side, and be fixed to the upper surface of the heat exchanger, a first screw to be arranged around the heat exchanger, and to fix the leaf spring to a printed circuit board, and a convex portion to be raised to be higher than a first portion of the first side and a second portion of the second side, and to be formed at a central portion between first and second portions within a region of the upper surface of the heat exchanger that overlaps with the leaf spring.Type: GrantFiled: February 1, 2019Date of Patent: February 25, 2020Assignee: FUJITSU LIMITEDInventors: Yoshiteru Ochi, Hidehisa Sakai
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Publication number: 20190281690Abstract: A cooling system includes a heat exchanger provided on a heat generating component, the heat exchanger having a size larger than the heat generating component, a leaf spring to extend from a first side of an upper surface of the heat exchanger to a second side opposite to the first side, and be fixed to the upper surface of the heat exchanger, a first screw to be arranged around the heat exchanger, and to fix the leaf spring to a printed circuit board, and a convex portion to be raised to be higher than a first portion of the first side and a second portion of the second side, and to be formed at a central portion between first and second portions within a region of the upper surface of the heat exchanger that overlaps with the leaf spring.Type: ApplicationFiled: February 1, 2019Publication date: September 12, 2019Applicant: FUJITSU LIMITEDInventors: Yoshiteru OCHI, Hidehisa Sakai
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Patent number: 9990445Abstract: In a meshing method for use in a computer-aided design (CAD) or computer-aided engineering (CAE) system, in which one or more serial meshing units are used to carry out a decoupled parallel meshing process in respect of all parts of a CAD assembly model, input parameters for the meshing process automatically, for each part to be processed, are set using live runtime information about the meshing process for the part concerned, such as information about the outcome of previous attempts to carry out the meshing process of the part.Type: GrantFiled: June 25, 2013Date of Patent: June 5, 2018Assignee: FUJITSU LIMITEDInventors: Serban Georgescu, Peter Chow, Makoto Sakairi, Hidehisa Sakai
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Publication number: 20180135920Abstract: An electronic device includes a heat exchanger that includes a flat tube through which fluid flows. The flat tube includes a tube main body section, a connecting wall portion, and a flange portion. The tube main body section has a join portion at which an outer face at one end side of the tube main body section and an inner face at another end side of the tube main body section are joined together in an overlapping state to form a flat tube shape. The connecting wall portion extends from the one end of the tube main body section toward the inside of the tube main body section. The flange portion extends along the inner face of the tube main body section from a leading end part of the connecting wall portion toward an opposite side from the join portion, and is joined to the inner face.Type: ApplicationFiled: October 16, 2017Publication date: May 17, 2018Applicant: FUJITSU LIMITEDInventors: Yoshiteru OCHI, Hidehisa Sakai, Tsuyoshi So, Hideo Kubo
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Patent number: 9471716Abstract: A disclosed setting method includes: in response to an instruction to replace a first component with a second component, determining whether or not data that correlates a surface of the first component with a surface of a third component has been set; upon determining that the data that correlates the surface of the first component with the surface of the third component has been set, extracting a surface of the second component, which corresponds to the surface of the first component; and correlating the extracted surface of the second component with the surface of the third component instead of the surface of the first component in the data.Type: GrantFiled: September 30, 2013Date of Patent: October 18, 2016Assignee: FUJITSU LIMITEDInventors: Takamasa Shinde, Makoto Sakairi, Kazuhisa Inagaki, Akihiko Fujisaki, Tetsuyuki Kubota, Sachiko Furuya, Hidehisa Sakai
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Patent number: 8816510Abstract: A semiconductor apparatus including: a substrate; and a semiconductor chip mounted on the substrate, wherein the substrate has plural holes, and the plural holes are provided such that the density on a substrate surface of the holes in a first area, which is an area of the substrate facing a semiconductor chip peripheral portion, is higher than the density on the substrate surface of the holes in an area excluding the first area on the substrate.Type: GrantFiled: September 28, 2009Date of Patent: August 26, 2014Assignee: Fujitsu LimitedInventors: Noriyuki Matsui, Hidehisa Sakai
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Publication number: 20140142899Abstract: A disclosed setting method includes: in response to an instruction to replace a first component with a second component, determining whether or not data that correlates a surface of the first component with a surface of a third component has been set; upon determining that the data that correlates the surface of the first component with the surface of the third component has been set, extracting a surface of the second component, which corresponds to the surface of the first component; and correlating the extracted surface of the second component with the surface of the third component instead of the surface of the first component in the data.Type: ApplicationFiled: September 30, 2013Publication date: May 22, 2014Applicant: FUJITSU LIMITEDInventors: Takamasa Shinde, Makoto Sakairi, Kazuhisa Inagaki, Akihiko Fujisaki, Tetsuyuki Kubota, Sachiko Furuya, Hidehisa Sakai
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Publication number: 20140039847Abstract: In a meshing method for use in a computer-aided design (CAD) or computer-aided engineering (CAE) system, in which one or more serial meshing units are used to carry out a decoupled parallel meshing process in respect of all parts of a CAD assembly model, input parameters for the meshing process automatically, for each part to be processed, are set using live runtime information about the meshing process for the part concerned, such as information about the outcome of previous attempts to carry out the meshing process of the part.Type: ApplicationFiled: June 25, 2013Publication date: February 6, 2014Inventors: Serban GEORGESCU, Peter CHOW, Makoto SAKAIRI, Hidehisa SAKAI
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Patent number: 8204699Abstract: An analyzing method includes acquiring displacements with respect to loads applied of the test piece measured by the three-point bending test; calculating a first approximate expression of a relation of the displacements with respect to the loads applied in a first area where the relation is linear so as to determine an elasticity modulus of the test piece; extracting boundary value of a relation of strains caused by the displacements with respect to the loads so as to determine a yield stress value of the test piece; and calculating a second approximate expression of a relation of stress caused by the loads with respect to the strains caused by the displacements in a second area beyond the yield stress value on the basis of the yield stress value, the elasticity modulus, and the measurements in the second area.Type: GrantFiled: January 29, 2010Date of Patent: June 19, 2012Assignee: Fujitsu LimitedInventor: Hidehisa Sakai
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Patent number: 8190378Abstract: An element damage determination unit calculates a cumulative value of a damage value using a Manson-Coffin law for a plurality of finite elements of a continuum based on a result of a stress/distortion analyzing process, and determines whether or not the cumulative value of the damage value is equal to or exceeds a threshold. A calculation unit obtains first correspondence information indicating the correspondence between the number of cycles of a load and a growth rate of a crack occurring in the continuum based on the determination result. A Manson-Coffin law change unit changes a Manson-Coffin law based on the first correspondence information and second correspondence information indicating the correspondence between an actual measurement value of the number of cycles of a load applied to the continuum and an actual measurement value of the growth rate of a crack occurring in the continuum at that time.Type: GrantFiled: October 30, 2008Date of Patent: May 29, 2012Assignee: Fujitsu LimitedInventors: Hidehisa Sakai, Katsufumi Morimune, Masanori Motegi, Tsutomu Iikawa
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Patent number: 7873501Abstract: The analysis model generation unit generates an analysis model for use in an analysis by a finite-element method. A stress distortion analysis unit analyzes a stress and a distortion occurring in finite elements of a continuum by a load using the analysis model for each load cycle cyclically applied to the continuum by the finite-element method. An element damage evaluation unit evaluates a damage by the distortion on the finite elements of the continuum based on the analysis result for each load cycle. A crack growth display unit displays the growth of a crack occurring in the continuum based on a result of the evaluation of the damage.Type: GrantFiled: November 15, 2007Date of Patent: January 18, 2011Assignee: Fujitsu LimitedInventor: Hidehisa Sakai
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Publication number: 20100204932Abstract: An analyzing method includes acquiring displacements with respect to loads applied of the test piece measured by the three-point bending test; calculating a first approximate expression of a relation of the displacements with respect to the loads applied in a first area where the relation is linear so as to determine an elasticity modulus of the test piece; extracting boundary value of a relation of strains caused by the displacements with respect to the loads so as to determine a yield stress value of the test piece; and calculating a second approximate expression of a relation of stress caused by the loads with respect to the strains caused by the displacements in a second area beyond the yield stress value on the basis of the yield stress value, the elasticity modulus, and the measurements in the second area.Type: ApplicationFiled: January 29, 2010Publication date: August 12, 2010Applicant: FUJITSU LIMITEDInventor: Hidehisa SAKAI
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Patent number: 7773814Abstract: The distortion of each node is calculated from the distortions of respective elements in the finite element analysis result of a global model of a structure, and a second-order coefficient of a quadratic function representing the displacement at each node of a micro model is calculated from distortions of respective nodes. In addition, a constant term and a first-order coefficient of the quadratic function are calculated from the displacements of the respective nodes of the global model. Then, the displacement at each boundary node of the micro model is calculated using the obtained quadratic function and a finite element analysis of the micro model is performed.Type: GrantFiled: September 29, 2005Date of Patent: August 10, 2010Assignee: Fujitsu LimitedInventor: Hidehisa Sakai
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Patent number: 7725866Abstract: When reliability evaluation of the whole electronic package is performed, the time required for simulation is decreased, while solder connection parts, in particular, are accurately analyzed. The whole analysis model creating unit creates a solder connection part model which has the same volume, height, and connection area as the volume, height, and connection area of the solder connection part. By means of dividing the solder connection model into multiple meshes, the first mesh data for use in electronic package analysis is created.Type: GrantFiled: September 14, 2007Date of Patent: May 25, 2010Assignee: Fujitsu LimitedInventors: Yoko Kobayashi, Hidehisa Sakai, Yoshiteru Ochi
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Publication number: 20100078810Abstract: A semiconductor apparatus including: a substrate; and a semiconductor chip mounted on the substrate, wherein the substrate has plural holes, and the plural holes are provided such that the density on a substrate surface of the holes in a first area, which is an area of the substrate facing a semiconductor chip peripheral portion, is higher than the density on the substrate surface of the holes in an area excluding the first area on the substrate.Type: ApplicationFiled: September 28, 2009Publication date: April 1, 2010Applicant: FUJITSU LIMITEDInventors: Noriyuki Matsui, Hidehisa Sakai
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Publication number: 20100053923Abstract: A semiconductor device that includes a semiconductor element, a package substrate, and a plurality of bonding members. The semiconductor element is fixed on the front surface of the package substrate. The package substrate has a first region and a second region on the back surface. The plurality of bonding members is arranged in a grid pattern on the first region of the back surface of the package substrate. The second region of the package substrate defines a bonding prohibition region corresponding with the periphery of the semiconductor element in a plan view.Type: ApplicationFiled: June 17, 2009Publication date: March 4, 2010Applicant: FUJITSU LIMITEDInventors: Noriyuki Matsui, Hidehisa Sakai
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Publication number: 20090187353Abstract: An element damage determination unit calculates a cumulative value of a damage value using a Manson-Coffin law for a plurality of finite elements of a continuum based on a result of a stress/distortion analyzing process, and determines whether or not the cumulative value of the damage value is equal to or exceeds a threshold. A calculation unit obtains first correspondence information indicating the correspondence between the number of cycles of a load and a growth rate of a crack occurring in the continuum based on the determination result. A Manson-Coffin law change unit changes a Manson-Coffin law based on the first correspondence information and second correspondence information indicating the correspondence between an actual measurement value of the number of cycles of a load applied to the continuum and an actual measurement value of the growth rate of a crack occurring in the continuum at that time.Type: ApplicationFiled: October 30, 2008Publication date: July 23, 2009Applicants: FUJITSU LIMITED, FUJITSU TEN LIMITEDInventors: Hidehisa Sakai, Katsufumi Morimune, Masanori Motegi, Tsutomu Iikawa
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Patent number: 7467076Abstract: Reliability of an electronic package is predicted based on material type, shape and dimensions of the package and conditions for assessment thereof, and a modeling unit creates a simulation model based thereon. An executing unit uses the simulation model to execute a simulation under designated conditions and results of the simulation are stored in a database. The stored simulation is assessed according to the assessment criteria and the assessment results are stored in a database. A generating unit generates, as an assessment expression, an approximate expression which infers the results of assessment from the inputted parameters, on the assumption that a predetermined amount of results of assessment is preserved. An assessment predicting unit outputs the results of an assessment of a package in which an assessment expression has already been established, by using the assessment expression.Type: GrantFiled: August 25, 2006Date of Patent: December 16, 2008Assignee: Fujitsu LimitedInventor: Hidehisa Sakai
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Publication number: 20080172211Abstract: The analysis model generation unit generates an analysis model for use in an analysis by a finite-element method. A stress distortion analysis unit analyzes a stress and a distortion occurring in finite elements of a continuum by a load using the analysis model for each load cycle cyclically applied to the continuum by the finite-element method. An element damage evaluation unit evaluates a damage by the distortion on the finite elements of the continuum based on the analysis result for each load cycle. A crack growth display unit displays the growth of a crack occurring in the continuum based on a result of the evaluation of the damage.Type: ApplicationFiled: November 15, 2007Publication date: July 17, 2008Applicant: FUJITSU LIMITEDInventor: Hidehisa Sakai
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Publication number: 20080127011Abstract: When reliability evaluation of the whole electronic package is performed, the time required for simulation is decreased, while solder connection parts, in particular, are accurately analyzed. The whole analysis model creating unit creates a solder connection part model which has the same volume, height, and connection area as the volume, height, and connection area of the solder connection part. By means of dividing the solder connection model into multiple meshes, the first mesh data for use in electronic package analysis is created.Type: ApplicationFiled: September 14, 2007Publication date: May 29, 2008Applicant: FUJITSU LIMITEDInventors: Yoko KOBAYASHI, Hidehisa Sakai, Yoshiteru Ochi