Patents by Inventor Hidekatsu Onose
Hidekatsu Onose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9755014Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.Type: GrantFiled: September 28, 2016Date of Patent: September 5, 2017Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.Inventors: Kazuhiro Mochizuki, Hidekatsu Onose, Norifumi Kameshiro, Natsuki Yokoyama
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Publication number: 20170018605Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×107 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.Type: ApplicationFiled: September 28, 2016Publication date: January 19, 2017Inventors: Kazuhiro MOCHIZUKI, Hidekatsu ONOSE, Norifumi KAMESHIRO, Natsuki YOKOYAMA
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Patent number: 9478605Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.Type: GrantFiled: December 10, 2013Date of Patent: October 25, 2016Assignee: Hitachi Power Semiconductor Device, Ltd.Inventors: Kazuhiro Mochizuki, Hidekatsu Onose, Norifumi Kameshiro, Natsuki Yokoyama
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Publication number: 20160005810Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.Type: ApplicationFiled: December 10, 2013Publication date: January 7, 2016Inventors: Kazuhiro MOCHIZUKI, Hidekatsu ONOSE, Norifumi KAMESHIRO, Natsuki YOKOYAMA
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Patent number: 8816355Abstract: For suggesting a structure capable of achieving both a low start-up voltage and high breakdown voltage, a SiC vertical diode includes a cathode electrode, an n++ cathode layer, an n? drift layer on the n++ cathode layer, a pair of p+ regions, an n+ channel region formed between the n? drift layer and the p+ region and sandwiched between the pair of p+ regions, n++ anode regions and an anode electrode formed on the n++ anode regions and the p+ regions.Type: GrantFiled: April 7, 2011Date of Patent: August 26, 2014Assignee: Hitachi, Ltd.Inventor: Hidekatsu Onose
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Patent number: 8508258Abstract: A driver circuit that lowers the dependence of the loss in the wide gap semiconductor device upon the temperature is provided. A gate driver circuit for voltage driven power semiconductor switching device includes a power semiconductor switching device, a driver circuit for supplying a drive signal to a gate terminal of the switching device with reference to an emitter control terminal or a source control terminal of the switching device, and a unit for detecting a temperature of the switching device. The temperature of the power semiconductor switching device is detected, and a gate drive voltage or a gate drive resistance value is changed based on the detected temperature.Type: GrantFiled: January 25, 2007Date of Patent: August 13, 2013Assignee: Hitachi, Ltd.Inventors: Katsumi Ishikawa, Sunao Funakoshi, Kozo Sakamoto, Hidekatsu Onose
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Patent number: 8227831Abstract: A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.Type: GrantFiled: March 2, 2010Date of Patent: July 24, 2012Assignee: Renesas Electronics CorporationInventor: Hidekatsu Onose
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Patent number: 8049223Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.Type: GrantFiled: May 25, 2008Date of Patent: November 1, 2011Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Hidekatsu Onose
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Publication number: 20110248286Abstract: For suggesting a structure capable of achieving both a low start-up voltage and high breakdown voltage, a SiC vertical diode includes a cathode electrode, an n++ cathode layer, an n? drift layer on the n++ cathode layer, a pair of p+ regions, an n+ channel region formed between the n? drift layer and the p+ region and sandwiched between the pair of p+ regions, n++ anode regions and an anode electrode formed on the n++ anode regions and the p+ regions.Type: ApplicationFiled: April 7, 2011Publication date: October 13, 2011Inventor: Hidekatsu ONOSE
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Patent number: 7906796Abstract: In a bipolar device, such as transistor or a thyristor, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides, among other things, an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance.Type: GrantFiled: July 21, 2008Date of Patent: March 15, 2011Assignee: Hitachi, Ltd.Inventors: Kazuhiro Mochizuki, Hidekatsu Onose, Natsuki Yokoyama
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Publication number: 20100224885Abstract: A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.Type: ApplicationFiled: March 2, 2010Publication date: September 9, 2010Inventor: Hidekatsu ONOSE
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Patent number: 7768066Abstract: A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N+ type SiC substrate constituting a drain layer; an N? type SiC layer that is in contact with the drain layer and constitutes a drift layer; a P type body layer formed on the drift layer and being a semiconductor layer; an N+ type SiC layer constituting a source layer; a trench extending from the source layer to a predetermined location placed in the drift layer; a P type electric field relaxation region provided around and outside a bottom portion of the trench; and a channel region extending from the N+ type source layer to the P type electric field relaxation region and having an impurity concentration higher than that of the N? type drift layer and lower than that of the P type body layer.Type: GrantFiled: July 24, 2008Date of Patent: August 3, 2010Assignee: Hitachi, Ltd.Inventors: Hidekatsu Onose, Hiroyuki Takazawa
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Publication number: 20090057685Abstract: In a mesa type bipolar transistor or a thyristor, since carriers injected from an emitter layer or an anode layer to a base layer or a gate layer diffuse laterally and are recombined, reduction in the size and improvement for the switching frequency is difficult. In the invention, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance.Type: ApplicationFiled: July 21, 2008Publication date: March 5, 2009Inventors: Kazuhiro MOCHIZUKI, Hidekatsu Onose, Natsuki Yokoyama
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Publication number: 20090032821Abstract: A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N+ type SiC substrate constituting a drain layer; an N? type SiC layer that is in contact with the drain layer and constitutes a drift layer; a P type body layer formed on the drift layer and being a semiconductor layer; an N+ type SiC layer constituting a source layer; a trench extending from the source layer to a predetermined location placed in the drift layer; a P type electric field relaxation region provided around and outside a bottom portion of the trench; and a channel region extending from the N+ type source layer to the P type electric field relaxation region and having an impurity concentration higher than that of the N? type drift layer and lower than that of the P type body layer.Type: ApplicationFiled: July 24, 2008Publication date: February 5, 2009Inventors: Hidekatsu Onose, Hiroyuki Takazawa
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Publication number: 20090014719Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.Type: ApplicationFiled: May 25, 2008Publication date: January 15, 2009Inventors: Haruka Shimizu, Hidekatsu Onose
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Publication number: 20070252178Abstract: The present invention can maintain a blocking state, even at a low gate bias voltage, in a diode-containing type of junction FET, and achieves a large saturation current. The junction FET includes: an n+ SiC substrate 10 as a drain layer; an n? SiC layer 11 contiguous to the drain layer as a drift layer; an n+ SiC layer 12 formed on the drift layer as a source layer; trench grooves formed ranging from the source layer to a required depth of the drift layer and part of the drift layer as a channel region; and p-type polycrystalline Si formed in the trench grooves as gate regions. The gate region at one side of the channel is electrically shorted to a source electrode to form a p? emitter of a diode.Type: ApplicationFiled: April 26, 2007Publication date: November 1, 2007Inventor: Hidekatsu ONOSE
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Publication number: 20070221994Abstract: A driver circuit that lowers the dependence of the loss in the wide gap semiconductor device upon the temperature is provided. A gate driver circuit for voltage driven power semiconductor switching device includes a power semiconductor switching device, a driver circuit for supplying a drive signal to a gate terminal of the switching device with reference to an emitter control terminal or a source control terminal of the switching device, and a unit for detecting a temperature of the switching device. The temperature of the power semiconductor switching device is detected, and a gate drive voltage or a gate drive resistance value is changed based on the detected temperature.Type: ApplicationFiled: January 25, 2007Publication date: September 27, 2007Inventors: Katsumi Ishikawa, Sunao Funakoshi, Kozo Sakamoto, Hidekatsu Onose
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Patent number: 7256453Abstract: A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n? channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.Type: GrantFiled: January 18, 2005Date of Patent: August 14, 2007Assignee: Hitachi, Ltd.Inventors: Hidekatsu Onose, Atsuo Watanabe
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Publication number: 20070114574Abstract: An object of the present invention is to achieve both the high withstand voltage and the low on-resistance in a polycrystalline Si embedded gate SiC junction FET. n+ —SiC is formed as a drain layer; and n? —SiC which contacts an n+ drain layer is formed as a drift layer. By using n+ —SiC, which is formed on an n? drift layer, as a source layer, and by forming a trench from an n+ source layer up to a position having the specified depth of the n? drift layer, part of the n? drift layer is used as a channel region. As a result, in a junction FET including, as a gate region, p-type polycrystalline Si that is embedded in the trench, at least a side wall of the channel region contacts the p-type polycrystalline Si gate region without using oxidation film.Type: ApplicationFiled: November 15, 2006Publication date: May 24, 2007Inventor: Hidekatsu Onose
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Publication number: 20050218424Abstract: A semiconductor switching device for an inverter includes a first conductivity type, low impurity concentration, semiconductor substrate having a band gap equal to or greater than 2.0 eV, a first conductivity type first region formed in a first plane of the substrate having a resistance lower than the substrate, a first electrode formed in another plane of the first region, a first conductivity type second region formed in a second plane of the substrate, and a second electrode formed on the second region. A trench is formed in the second plane, a control region is formed from a bottom of the trench into the substrate and a control electrode of a different conductivity type is formed on the control region. The second electrode is formed over the control electrode through an insulator film, and the control electrode is formed on the trench sidewalls so the control region contacts the second region.Type: ApplicationFiled: May 24, 2005Publication date: October 6, 2005Inventors: Hidekatsu Onose, Hideo Homma, Atsuo Watanabe