Patents by Inventor Hidekazu Okuda
Hidekazu Okuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110212609Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: ApplicationFiled: May 6, 2011Publication date: September 1, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
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Patent number: 7977165Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: GrantFiled: December 22, 2009Date of Patent: July 12, 2011Assignee: Renesas Electronics CorporationInventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
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Patent number: 7776660Abstract: Provided is a technology of carrying out activation annealing of n type impurity ions implanted for the formation of a field stop layer (n+ type semiconductor region) and activation annealing of p type impurity ions implanted for the formation of a collector region (p+ type semiconductor region) in separate steps to adjust an activation ratio of the n type impurity ions in the field stop layer to 60% or greater and an activation ratio of the p type impurity ions in the collector region to from 1 to 15%. This makes it possible to form an IGBT having a high breakdown voltage and high-speed switching characteristics. Moreover, use of a film stack made of nickel silicide, titanium, nickel and gold films for a collector electrode makes it possible to provide an ohmic contact with the collector region.Type: GrantFiled: August 3, 2007Date of Patent: August 17, 2010Assignee: Renesas Technology Corp.Inventors: Isao Miyashita, Yuji Fujii, Hajime Ebara, Katsuo Ishizaka, Norio Hosoya, Hidekazu Okuda
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Publication number: 20100127306Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: ApplicationFiled: December 22, 2009Publication date: May 27, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
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Patent number: 7687907Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: GrantFiled: December 28, 2007Date of Patent: March 30, 2010Assignee: Renesas Technology Corp.Inventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
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Publication number: 20090174061Abstract: To prevent peeling-off of a film in a solder connection pad of a semiconductor device, which peeling-off may occur due to thermal load and so on in the manufacture process, a pad structure is adopted in which a Cr film good in adhesiveness to either of a Ti film or Ti compound film and a Ni film (or a Cu film) is interposed between the Ti film or Ti compound film formed on a silicon or silicon oxide film, and the Ni film (or the Cu film) to be connected to solder. Further, to prevent peeling-off at the interface between the Ti film or Ti compound film and the silicon oxide film, the Cr film is formed in a larger area than the Ti film or Ti compound film.Type: ApplicationFiled: March 10, 2009Publication date: July 9, 2009Applicant: Hitachi, Ltd.Inventors: Yasuhiro NAKA, Tomio Iwasaki, Hidekazu Okuda, Yuji Fujii
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Publication number: 20080105971Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: ApplicationFiled: December 28, 2007Publication date: May 8, 2008Inventors: Hidekazu OKUDA, Haruo Amada, Taizo Hashimoto
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Publication number: 20080076238Abstract: Provided is a technology of carrying out activation annealing of n type impurity ions implanted for the formation of a field stop layer (n+ type semiconductor region) and activation annealing of p type impurity ions implanted for the formation of a collector region (p+ type semiconductor region) in separate steps to adjust an activation ratio of the n type impurity ions in the field stop layer to 60% or greater and an activation ratio of the p type impurity ions in the collector region to from 1 to 15%. This makes it possible to form an IGBT having a high breakdown voltage and high-speed switching characteristics. Moreover, use of a film stack made of nickel silicide, titanium, nickel and gold films for a collector electrode makes it possible to provide an ohmic contact with the collector region.Type: ApplicationFiled: August 3, 2007Publication date: March 27, 2008Inventors: Isao Miyashita, Yuji Fujii, Hajime Ebara, Katsuo Ishizaka, Norio Hosoya, Hidekazu Okuda
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Patent number: 7335574Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: GrantFiled: April 7, 2005Date of Patent: February 26, 2008Assignee: Renesas Technology Corp.Inventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
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Publication number: 20060043605Abstract: To prevent peeling-off of a film in a solder connection pad of a semiconductor device, which peeling-off may occur due to thermal load and so on in the manufacture process, a pad structure is adopted in which a Cr film good in adhesiveness to either of a Ti film or Ti compound film and a Ni film (or a Cu film) is interposed between the Ti film or Ti compound film formed on a silicon or silicon oxide film, and the Ni film (or the Cu film) to be connected to solder. Further, to prevent peeling-off at the interface between the Ti film or Ti compound film and the silicon oxide film, the Cr film is formed in a larger area than the Ti film or Ti compound film.Type: ApplicationFiled: June 29, 2005Publication date: March 2, 2006Applicant: Renesas Technology Corp.Inventors: Yasuhiro Naka, Tomio Iwasaki, Hidekazu Okuda, Yuji Fujii
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Publication number: 20050233499Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.Type: ApplicationFiled: April 7, 2005Publication date: October 20, 2005Inventors: Hidekazu Okuda, Haruo Amada, Taizo Hashimoto
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Publication number: 20030157768Abstract: Disclosed is a method to achieve the planarization of a BPSG film and reduction of micro-scratches on a BPSG film by the CMP method. A BPSG film is deposited over a main surface of a substrate on which MISFETs have been formed, and then, a surface of the BPSG film is planarized by the CMP method. Thereafter, a thermal treatment is performed to the substrate to reflow the BPSG film, thereby removing the micro-scratches on the surface of the BPSG film caused by the polishing. At this time, the amount of polishing of the surface of the BPSG film is controlled within a range of 90 to 300 nm, preferably 100 to 250 nm, and more preferably 120 to 200 nm.Type: ApplicationFiled: February 13, 2003Publication date: August 21, 2003Applicant: Hitachi, Ltd.Inventors: Shinichi Nakabayashi, Hidekazu Okuda, Kosaku Tachikawa