Patents by Inventor Hideki Daian

Hideki Daian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10395344
    Abstract: A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: August 27, 2019
    Assignee: MegaChips Corporation
    Inventors: Hiroki Nakamori, Takuya Sawada, Hideki Daian
  • Publication number: 20180144444
    Abstract: A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image.
    Type: Application
    Filed: January 18, 2018
    Publication date: May 24, 2018
    Applicant: MegaChips Corporation
    Inventors: Hiroki NAKAMORI, Takuya Sawada, Hideki Daian
  • Publication number: 20180144445
    Abstract: A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image.
    Type: Application
    Filed: January 18, 2018
    Publication date: May 24, 2018
    Applicant: MegaChips Corporation
    Inventors: Hideki DAIAN, Takuya SAWADA
  • Patent number: 9916642
    Abstract: A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 13, 2018
    Assignee: MegaChips Corporation
    Inventors: Hiroki Nakamori, Takuya Sawada, Hideki Daian
  • Patent number: 9881361
    Abstract: A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 30, 2018
    Assignee: MegaChips Corporation
    Inventors: Hideki Daian, Takuya Sawada
  • Publication number: 20170103501
    Abstract: A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Applicant: MegaChips Corporation
    Inventors: Hiroki NAKAMORI, Takuya SAWADA, Hideki DAIAN
  • Publication number: 20170103500
    Abstract: A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Applicant: MegaChips Corporation
    Inventors: Hideki DAIAN, Takuya SAWADA
  • Patent number: 9552628
    Abstract: A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: January 24, 2017
    Assignee: MegaChips Corporation
    Inventors: Hideki Daian, Takuya Sawada
  • Patent number: 9516320
    Abstract: Search is performed on Intra 16 to obtain a prediction mode leading to a minimum cost, and the minimum cost in Intra 16 and a corresponding prediction mode are stored. Search is performed on Intra 8 to obtain a prediction mode leading to a minimum cost, and then a relationship of magnitude between the stored minimum cost in Intra 16 and the minimum cost in Intra 8 is judged. After that, the minimum cost in Intra 8 and a corresponding prediction mode are stored, and search is performed on Intra 4 to obtain a prediction mode leading to a minimum cost. A relationship of magnitude between cost_intra and the minimum cost in Intra 4 is judged, and Intra 4 is determined as an optimum prediction mode in a case where Intra 4 is smaller.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: December 6, 2016
    Assignee: MegaChips Corporation
    Inventor: Hideki Daian
  • Patent number: 9471965
    Abstract: A first edge strength calculation circuit calculates an edge strength of each pixel in the image on the basis of results of detection by the first edge detection circuit. A filter strength setting unit sets a filter strength of a two-dimensional lowpass filter for each pixel, on the basis of the edge strength calculated by the edge strength calculation circuit. A second edge strength calculation circuit calculates an edge strength of each pixel in the image, on the basis of results of detection by the second edge detection circuit. An enhancement strength setting circuit sets an edge enhancement strength of the edge enhancement filter for each pixel, on the basis of the edge strength calculate by the second edge strength calculation circuit.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: October 18, 2016
    Assignee: MegaChips Corporation
    Inventors: Akira Okamoto, Takuya Sawada, Hideki Daian
  • Patent number: 9307244
    Abstract: A data storage controlling device has: a compression unit which performs lossless compression on each compression object region; determination means which determines whether or not the lossless compression is possible in each compression determination region including a plurality of compression object regions; and a storage control unit which performs storage control in each compression determination region in such a manner that data after the lossless compression in a compression determination region is stored as compressed data into a storage unit when it is determined that the lossless compression in each compression object region included in the certain compression determination region is possible, and image data before the lossless compression in the certain compression determination region is stored into the storage unit when it is determined that the lossless compression in each compression object region included in the certain compression determination region is impossible.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 5, 2016
    Assignee: MegaChips Corporation
    Inventors: Tomoaki Madanbashi, Akira Okamoto, Hideki Daian
  • Publication number: 20160093027
    Abstract: A first edge strength calculation circuit calculates an edge strength of each pixel in the image on the basis of results of detection by the first edge detection circuit. A filter strength setting unit sets a filter strength of a two-dimensional lowpass filter for each pixel, on the basis of the edge strength calculated by the edge strength calculation circuit. A second edge strength calculation circuit calculates an edge strength of each pixel in the image, on the basis of results of detection by the second edge detection circuit. An enhancement strength setting circuit sets an edge enhancement strength of the edge enhancement filter for each pixel, on the basis of the edge strength calculate by the second edge strength calculation circuit.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 31, 2016
    Applicant: MegaChips Corporation
    Inventors: Akira OKAMOTO, Takuya SAWADA, Hideki DAIAN
  • Publication number: 20150262340
    Abstract: A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 17, 2015
    Applicant: MegaChips Corporation
    Inventors: Hideki DAIAN, Takuya Sawada
  • Patent number: 8818123
    Abstract: A technique for eliminating the unnaturalness in a generated moving image while achieving high speed processing in an image processing apparatus which includes a deblocking filter is provided. A transcoder includes an MPEG2 decoder, a strength evaluation circuit, and an H.264 encoder. The strength evaluation circuit calculates a filter strength parameter on the basis of an image feature value parameter acquired by the MPEG2 decoder. The H.264 encoder applies a deblocking filter to an input image on the basis of the filter strength parameter in a coding process. The H.264 encoder codes a picture while the strength evaluation circuit performs a filter strength calculation process on a subsequent picture concurrently.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: August 26, 2014
    Assignee: MegaChips Corporation
    Inventor: Hideki Daian
  • Publication number: 20140044371
    Abstract: A data storage controlling device has: a compression unit which performs lossless compression on each compression object region; determination means which determines whether or not the lossless compression is possible in each compression determination region including a plurality of compression object regions; and a storage control unit which performs storage control in each compression determination region in such a manner that data after the lossless compression in a compression determination region is stored as compressed data into a storage unit when it is determined that the lossless compression in each compression object region included in the certain compression determination region is possible, and image data before the lossless compression in the certain compression determination region is stored into the storage unit when it is determined that the lossless compression in each compression object region included in the certain compression determination region is impossible.
    Type: Application
    Filed: July 26, 2013
    Publication date: February 13, 2014
    Applicant: MegaChips Corporation
    Inventors: Tomoaki MADANBASHI, Akira OKAMOTO, Hideki DAIAN
  • Patent number: 8369634
    Abstract: A sorting unit sorts a plurality of data sets of HP component having been processed by a decoding unit, selectively employing one of a first table corresponding to a first orientation of prediction and a second table corresponding to a second orientation of prediction in accordance with an orientation of prediction of HP component. The sorting unit includes an inverse prediction unit performing inverse prediction on data of LP component inputted from the decoding unit, a processing unit obtaining an orientation of prediction of HP component, based on the data of LP component after inverse prediction by the inverse prediction unit, and a selecting unit selecting one of the first and second tables, based on the orientation of prediction of HP component obtained by the processing unit.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: February 5, 2013
    Assignee: MegaChips Corporation
    Inventors: Nobuhiro Minami, Yujiro Tani, Yusuke Mizuno, Hideki Daian, Masahiro Moriyama, Hiromu Hasegawa
  • Patent number: 8160376
    Abstract: An image compression apparatus performs quantization of DC component data, low-pass component data and high-pass component data which are generated by frequency conversion of still image data. An extracting part extracts additional data and coding object data which is to be entropy coded, from quantization data. An entropy coding part performs entropy coding of the coding object data stored in a coding object data memory. An additional data processing part generates a flex bit from the additional data. A pattern information generation part acquires the coding object data directly from the extracting part, to generate pattern information indicating whether the coding object data is zero or not. A bit stream generation part outputs the pattern information, the coding object data and the flex bit in a predetermined order, to output a bit stream.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: April 17, 2012
    Assignee: MegaChips Corporation
    Inventors: Masahiro Moriyama, Yujiro Tani, Yusuke Mizuno, Hideki Daian, Nobuhiro Minami, Hiromu Hasegawa
  • Patent number: 8160377
    Abstract: A symbol generation part serially inputs a data string of quantization data. If quantization data of non-zero coefficient is inputted, respective information on an absolute value, a zero run and a sign of the non-zero coefficient are stored in registers. When quantization data of the next non-zero coefficient is inputted, the respective information on the absolute value, the zero run and the sign stored in the registers are updated. At that time, the contents of the registers which have been stored immediately before the input are outputted as symbol data of the immediately preceding non-zero coefficient.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: April 17, 2012
    Assignee: MegaChips Corporation
    Inventors: Yujiro Tani, Yusuke Mizuno, Hideki Daian, Nobuhiro Minami, Masahiro Moriyama, Hiromu Hasegawa
  • Patent number: 8107746
    Abstract: A decoding unit includes a first processing unit including ND decoding units and decoding a group of Normal Data, a second processing unit decoding a group of Flex Bits, and a selector. The ND decoding units perform decoding of the group of Normal Data, stepwise varying a start position of decoding in the data stream, concurrently with decoding of the group of Flex Bits by the second processing unit. The selector selects one ND decoding unit with a start position of decoding being set at a position immediately following an end position of the group of Flex Bits, from the ND decoding units, based on a result of decoding of the group of Flex Bits.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: January 31, 2012
    Assignee: MegaChips Corporation
    Inventors: Hideki Daian, Yujiro Tani, Yusuke Mizuno, Nobuhiro Minami, Masahiro Moriyama, Hiromu Hasegawa
  • Publication number: 20110268366
    Abstract: It is an object of the present invention to provide a technique for eliminating the unnaturalness in a generated moving image while achieving high speed processing in an image processing apparatus comprising a deblocking filter. A transcoder (1) comprises an MPEG2 decoder (2), a strength evaluation circuit (3), and an H.264 encoder (4). The strength evaluation circuit (3) calculates a filter strength parameter (104) on the basis of an image feature value parameter (103) acquired by the MPEG2 decoder (2). The H.264 encoder (4) applies a deblocking filter to an input image on the basis of the filter strength parameter (104) in a coding process. The H.264 encoder (4) codes a picture while the strength evaluation circuit (3) performs a filter strength calculation process on a subsequent picture concurrently.
    Type: Application
    Filed: March 24, 2009
    Publication date: November 3, 2011
    Applicant: MEGACHIPS CORPORATION
    Inventor: Hideki Daian