Abstract: A semiconductor storage device of an embodiment includes a memory block, a resistance measurement circuit, and a control circuit. The memory block includes first to third control signal lines connected to gates of a first select gate transistor, a plurality of memory cell transistors, and a second select gate transistor. The resistance measurement circuit measures resistance of at least one control signal line among the first to third control signal lines. The control circuit performs erase, program, and read of data at the plurality of memory cell transistors included in the memory block. The control circuit determines, based on a measurement result of the resistance measurement by the resistance measurement circuit, whether to set a fail status to a result of erase verify that verifies the erase.

Abstract: Provided is a display control system including at least one processor configured to: acquire information received by a user; determine whether the information satisfies a display condition associated with each of a plurality of display areas on a display screen; and display the display screen such that, in each of the plurality of display areas, the information determined to satisfy the display condition associated with the display area is arranged.

Abstract: Provided is a task support system for supporting a user in tasks, the task support system including at least one processor configured to: display a notification screen relating to a notification received by the user in the task support system; receive, on the notification screen, a first operation relating to a notification-related task associated with the notification; and execute first task processing relating to the notification-related task based on the first operation.

Abstract: A semiconductor memory device performs: an erase voltage supply operation that applies an erase voltage to a first wiring; a first erase verify operation that applies a read pass voltage to a first conductive layer, and applies an erase verify voltage to a second conductive layer after performing the erase voltage supply operation; and a second erase verify operation that applies the erase verify voltage to the first conductive layer, and applies the read pass voltage to the second conductive layer after performing the first erase verify operation. The erase voltage increases by a first offset voltage in each erase loop from a first erase loop to an a-th erase loop, and the erase voltage increases by a second offset voltage in each erase loop from an a+1-th erase loop to a b-th erase loop. The second offset voltage is larger than the first offset voltage.

Abstract: A semiconductor storage device of an embodiment includes a memory block, a resistance measurement circuit, and a control circuit. The memory block includes first to third control signal lines connected to gates of a first select gate transistor, a plurality of memory cell transistors, and a second select gate transistor. The resistance measurement circuit measures resistance of at least one control signal line among the first to third control signal lines. The control circuit performs erase, program, and read of data at the plurality of memory cell transistors included in the memory block. The control circuit determines, based on a measurement result of the resistance measurement by the resistance measurement circuit, whether to set a fail status to a result of erase verify that verifies the erase.

Abstract: A diversity receiver includes: a differential detection diversity reception circuit for performing a diversity reception with employment of a differential detection to thereby output hard decision data thereof; a least-squares combining diversity reception circuit for performing a least-squares combining diversity reception to thereby output differentially decoded result of the hard decision data; a selection control circuit for producing a selection control signal used to select one of the hard decision data outputted from the differential detection diversity reception circuit and the differentially decoded result outputted from the least-squares combining diversity reception circuit based upon a predetermined selection basis; and a selection circuit for selecting one of the hard decision data and the differentially decoded result based upon the selection control signal.

Abstract: An adaptive equalizer includes a channel memory length estimator (41) for estimating a channel memory length of a received signal, an adaptive equalizer (42) for reducing effect of intersymbol interference on the received signal using a technique suitable for a channel with a fast time-varying characteristic, an adaptive equalizer (43) for reducing effect of intersymbol interference on the received signal using a technique suitable for a channel with a large delay spread, and a selector for switching, in response to the channel memory length supplied from the channel memory length estimator (41), between the adaptive equalizer (42) suitable for the channel with the fast time-varying characteristic and the adaptive equalizer (43) suitable for the channel with the large delay spread, thereby implementing good bit error rate performance.

Abstract: A soft decision decoder including an adaptive equalizer and a reliability information generator. The reliability information generator, receiving soft decision data and equalized square error from the adaptive filter, performs delay detection of the soft decision data, and then rotates the phase of the delay detected data so as to match the data to transmitted data components. The rotated data is weighted with the average value of the equalized square error to generate the reliability information for the soft decision Viterbi decoding. This makes it possible to obviate the exponential or logarithm calculations which are conventionally needed for generating the reliability information for carrying out the soft decision Viterbi decoding of the output of the adaptive equalizer, and hence to reduce the enormous amount of calculations and the size of hardware like DSP for performing the calculations.

Abstract: A refractory brick for a glass fusion furnace includes a triangular hollow-prism type brick body (1) having a flow passage (1c) formed so as to extend between two opposite ends of the brick. The flow passage (1c) has a substantially triangular cross-section.