Abstract: An image processing apparatus includes a partial image memory unit for reading partial image data from an image pickup device and sequentially storing the partial image data, and an image composition unit for generating the composite image data by synthesizing the partial image data from the partial image memory unit. Only when a composition incomplete signal does not exist, the partial image memory unit stores the partial image data and generates a storage completion signal upon completing storage of the partial image data. The image composition unit generates the composition incomplete signal when the composite image data is generated, on condition that the storage completion signal is present. The image composition unit reads at least one of the partial image data from the partial image memory unit and starts the generation of the composite image data using the partial image data when the composite image data is not generated.

Abstract: An image processing apparatus includes a partial image memory unit for reading partial image data from an image pickup device and sequentially storing the partial image data. The image processing apparatus also includes an image composition unit for generating the composite image data by synthesizing the partial image data obtained from the partial image memory unit. Only when a composition incomplete signal does not exists the partial image memory unit stores the partial image data and generates a storage completion signal upon completing the storage of the partial image data. The image composition unit generates the composition incomplete signal when the composite image data is being generated, on the condition that the storage completion signal is present. The image composition unit reads at least one of the partial image data from the partial image memory unit and starts the generation of the composite image data using the partial image data when the composite image data is not being generated.

Abstract: The present invention provides a multilayered bus system capable of performing transition to a power-saving mode reliably and rapidly. When a mode designation signal for designating the power-saving mode is outputted from a clock controller in response to mode setting information outputted from a CPU, respective arbiters respectively output response signals for prohibiting access to bus slaves to their corresponding bus masters. When the power-saving mode is designated by the mode designation signal, the response signal for prohibiting access is outputted from the arbiter, and an end signal indicating that the respective bus slaves do not perform data transfers for a predetermined period of time is outputted from a monitor, a control signal for stopping the supply of a system clock is outputted from the clock controller to a clock generator.

Abstract: A multi-layer bus system includes an interconnect matrix, bus slaves, bus masters and a bus control circuit. The interconnect matrix has master connection ports and slave connection ports, and connects one of the master connection ports to one of the slave connection ports in response a control signal. The slaves are connected to the slave connection ports, respectively. The bus masters includes a priority bus master connected to one of the master connection ports and a non-priority bus master. The priority bus master generates a bus demand signal when it needs a real-time operation. The bus control circuit is connected between the non-priority bus master and the other master connection ports. The bus control circuit disconnects the non-priority bus master to the other master connection ports in response to the bus demand signal.

Abstract: An address decoder 10 decodes an address signal 20 to generate access signals 22, 24. An OR circuit implements a logical OR of the signals 22, 24 to generate a chip enable signal. An address generation circuit 14 generates an address signal 28 to access the RAM in ascending order from a head address based upon the signal 20. An address inversion circuit 16 inverts and outputs each bit of the signal 28 when the signal 24 is “1” or outputs the address signal without inversion when the signal 24 is “0.” When the chip enable signal is “1,” the RAM performs reading/writing data according to an address signal 30 from the inversion circuit.

Abstract: A two-dimensional fast Fourier transform is carried out on a block of sample points by executing a one-dimensional fast Fourier transform on all vertical lines of sample points, storing the resulting values at one or more specified positions in each vertical line in an internal buffer, and then executing a one-dimensional fast Fourier transform on each resulting horizontal line of transformed data. This entire process is repeated, the specified positions being changed at each repetition, until all horizontal lines have been processed. The necessary amount of buffer memory is reduced because the internal buffer only has to store intermediate results for a limited number of horizontal lines.

Abstract: A multi-layer bus system includes an interconnect matrix, bus slaves, bus masters and a bus control circuit. The interconnect matrix has master connection ports and slave connection ports, and connects one of the master connection ports to one of the slave connection ports in response a control signal. The slaves are connected to the slave connection ports, respectively. The bus masters includes a priority bus master connected to one of the master connection ports and a non-priority bus master. The priority bus master generates a bus demand signal when it needs a real-time operation. The bus control circuit is connected between the non-priority bus master and the other master connection ports. The bus control circuit disconnects the non-priority bus master to the other master connection ports in response to the bus demand signal.

Abstract: An address decoder 10 decodes an address signal 20 to generate access signals 22, 24. An OR circuit implements a logical OR of the signals 22, 24 to generate a chip enable signal. An address generation circuit 14 generates an address signal 28 to access the RAM in ascending order from a head address based upon the signal 20. An address inversion circuit 16 inverts and outputs each bit of the signal 28 when the signal 24 is “1” or outputs the address signal without inversion when the signal 24 is “0.” When the chip enable signal is “1,” the RAM performs reading/writing data according to an address signal 30 from the inversion circuit.