Patents by Inventor Hideki Kanayama
Hideki Kanayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230418772Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.Type: ApplicationFiled: June 24, 2022Publication date: December 28, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Hideki Kanayama, YuBin Yao
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Publication number: 20230102680Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Hideki Kanayama, Eric M. Scott
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Publication number: 20230004400Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.Type: ApplicationFiled: September 13, 2022Publication date: January 5, 2023Inventors: JYOTI RAHEJA, HIDEKI KANAYAMA, GUHAN KRISHNAN, RUIHUA PENG
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Patent number: 11449346Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.Type: GrantFiled: December 18, 2019Date of Patent: September 20, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Jyoti Raheja, Hideki Kanayama, Guhan Krishnan, Ruihua Peng
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Publication number: 20210191737Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Jyoti Raheja, Hideki Kanayama, Guhan Krishnan, Ruihua Peng
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Patent number: 10684969Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.Type: GrantFiled: July 15, 2016Date of Patent: June 16, 2020Assignee: Advanced Micro Devices, Inc.Inventors: James R. Magro, Kedarnath Balakrishnan, Jackson Peng, Hideki Kanayama
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Patent number: 10403333Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.Type: GrantFiled: July 15, 2016Date of Patent: September 3, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Kevin M. Brandl, Thomas Hamilton, Hideki Kanayama, Kedarnath Balakrishnan, James R. Magro, Guanhao Shen, Mark Fowler
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Publication number: 20180018291Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.Type: ApplicationFiled: July 15, 2016Publication date: January 18, 2018Applicant: Advanced Micro Devices, Inc.Inventors: James R. Magro, Kedarnath Balakrishnan, Jackson Peng, Hideki Kanayama
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Publication number: 20180019006Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.Type: ApplicationFiled: July 15, 2016Publication date: January 18, 2018Applicant: Advanced Micro Devices, Inc.Inventors: Kevin M. Brandl, Thomas Hamilton, Hideki Kanayama, Kedarnath Balakrishnan, James R. Magro, Guanhao Shen, Mark Fowler
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Patent number: 6147633Abstract: In a delta-sigma type analog-to-digital converter, an offset varying during operation is removed, and a reduction in time required to generate a stable value after powering on the converter is achieved. A high pass filter is provided with a variable filter coefficient which can vary during operation. A filter coefficient controller supplies a coefficient control signal to the high pass filter to change the variable filter coefficient during operation, thereby altering the time constant of the high pass filter.Type: GrantFiled: May 14, 1998Date of Patent: November 14, 2000Assignee: Burr-Brown CorporationInventors: Masayuki Ukawa, Hideki Kanayama
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Patent number: 5835038Abstract: A characteristic tone in a delta-sigma analog-to-digital converter is shifted out of an audible pass band without diminishing dynamic range or signal-to-noise ratio thereof by operating the digital-to-analog converter to measure its offset voltage. If the amplitude of the measured offset voltage exceeds a predetermined value, no dither signal is applied to the input of the delta-sigma modulator. If the measured offset voltage is less than the predetermined value, a positive DC dither voltage is added to the input voltage of the delta-sigma modulator if the measured offset voltage is positive, or is subtracted if the measured offset voltage is negative.Type: GrantFiled: May 8, 1997Date of Patent: November 10, 1998Assignee: Burr-Brown CorporationInventors: Shigetoshi Nakao, Hideki Kanayama, Toshio Murota, Masayuki Ukawa