Patents by Inventor Hideki Kato
Hideki Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10277845Abstract: There is provided a method of driving a solid-state imaging device, the solid-state imaging device including a plurality of column circuits which are arranged for each column of pixels and an amplification and selection circuit configured to amplify a differential signal based on a column pixel signal and a column reset signal, the method including causing the amplification and selection circuit to perform at least two operations among a first operation of sampling the column pixel signal, a second operation of sampling the column reset signal, and a third operation of output the amplified differential signal in parallel in the same period; and causing components connected to different horizontal signal lines to perform operations corresponding to the first to third operation in that order, and causing the components to perform different operations in parallel in the same period with respect to the first to third operations.Type: GrantFiled: February 22, 2018Date of Patent: April 30, 2019Assignee: OLYMPUS CORPORATIONInventors: Hideki Kato, Yasunari Harada, Masato Osawa
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Patent number: 10194110Abstract: This solid-state imaging device includes a first substrate and a second substrate which have circuit elements constituting pixels disposed therein are electrically connected to each other. The pixels includes: a photoelectric conversion element disposed in the first substrate; an amplifier circuit that amplifies a signal generated in the photoelectric conversion element to output the amplified signal; a signal accumulation circuit which is disposed in the second substrate and accumulates the amplified signal which is output from the amplifier circuit; and an output circuit that outputs the amplified signal accumulated in the signal accumulation circuit from the pixel.Type: GrantFiled: December 28, 2017Date of Patent: January 29, 2019Assignee: OLYMPUS CORPORATIONInventors: Yuichi Gomi, Hideki Kato, Naofumi Sakaguchi, Naoto Fukuoka
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Publication number: 20180367160Abstract: In an AD converter, a first DAC circuit performs a first operation in parallel with a second operation performed by a second DAC circuit, and the first DAC circuit performs the second operation in parallel with the first operation performed by the second DAC circuit. In the first operation, electric charge corresponding to an input signal of the first DAC circuit or an input signal of the second DAC circuit is sampled. In the second operation, an AD conversion is sequentially performed on the basis of the electric charge sampled in the first operation. The first DAC circuit and the second DAC circuit alternately perform the first operation and the second operation.Type: ApplicationFiled: August 17, 2018Publication date: December 20, 2018Applicant: OLYMPUS CORPORATIONInventors: Masato Osawa, Yasunari Harada, Shuzo Hiraide, Hideki Kato
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Publication number: 20180358977Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Applicant: OLYMPUS CORPORATIONInventors: Hideki Kato, Yasunari Harada, Shuzo Hiraide, Masato Osawa
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Publication number: 20180351568Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.Type: ApplicationFiled: August 10, 2018Publication date: December 6, 2018Applicant: OLYMPUS CORPORATIONInventors: Shuzo Hiraide, Yasunari Harada, Masato Osawa, Hideki Kato
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Publication number: 20180331688Abstract: A successive approximation type A/D conversion circuit includes a first capacitor circuit, a second capacitor circuit, a plurality of comparison circuits, a determination circuit, and a control circuit. The determination circuit counts a first number of first state and a second number of second state with respect to a plurality of first digital signals output from the plurality of comparison circuits. The determination circuit outputs a control signal for stopping the plurality of comparison circuits to the control circuit when an absolute value of a difference between the first number and the second number is equal to or smaller than 1. The control circuit stops the plurality of comparison circuits on the basis of the control signal.Type: ApplicationFiled: July 24, 2018Publication date: November 15, 2018Applicant: OLYMPUS CORPORATIONInventors: Yasunari Harada, Shuzo Hiraide, Masato Osawa, Hideki Kato
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Publication number: 20180184026Abstract: There is provided a method of driving a solid-state imaging device, the solid-state imaging device including a plurality of column circuits which are arranged for each column of pixels and an amplification and selection circuit configured to amplify a differential signal based on a column pixel signal and a column reset signal, the method including causing the amplification and selection circuit to perform at least two operations among a first operation of sampling the column pixel signal, a second operation of sampling the column reset signal, and a third operation of output the amplified differential signal in parallel in the same period; and causing components connected to different horizontal signal lines to perform operations corresponding to the first to third operation in that order, and causing the components to perform different operations in parallel in the same period with respect to the first to third operations.Type: ApplicationFiled: February 22, 2018Publication date: June 28, 2018Applicant: OLYMPUS CORPORATIONInventors: Hideki Kato, Yasunari Harada, Masato Osawa
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Patent number: 9979364Abstract: In a semiconductor device, a first variable gain amplifier and a second variable gain amplifier constitute a switched capacitor type variable gain amplifier. A selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and a load circuit such that the first variable gain amplifier and the load circuit are connected to each other when an amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain.Type: GrantFiled: October 19, 2017Date of Patent: May 22, 2018Assignee: OLYMPUS CORPORATIONInventors: Masato Osawa, Yasunari Harada, Hideki Kato
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Publication number: 20180124347Abstract: This solid-state imaging device includes a first substrate and a second substrate which have circuit elements constituting pixels disposed therein are electrically connected to each other. The pixels includes: a photoelectric conversion element disposed in the first substrate; an amplifier circuit that amplifies a signal generated in the photoelectric conversion element to output the amplified signal; a signal accumulation circuit which is disposed in the second substrate and accumulates the amplified signal which is output from the amplifier circuit; and an output circuit that outputs the amplified signal accumulated in the signal accumulation circuit from the pixel.Type: ApplicationFiled: December 28, 2017Publication date: May 3, 2018Applicant: OLYMPUS CORPORATIONInventors: Yuichi Gomi, Hideki Kato, Naofumi Sakaguchi, Naoto Fukuoka
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Publication number: 20180102768Abstract: A semiconductor device is provided that includes an amplification circuit, a downstream circuit, and a clipping circuit. The amplification circuit includes a sampling capacitor, a feedback capacitor, and an operational amplifier circuit. The sampling capacitor holds air input signal on which sampling is performed, as a signal whose reference is a first reference voltage. The signal that is held in the sampling capacitor is transferred to the feedback capacitor. The operational amplifier circuit amplifies the signal that is held in the sampling capacitor, according to a ratio between values of the sampling capacitor and the feedback capacitor, and outputs the amplified signal, as a signal whose reference is a second reference voltage. The clipping circuit limits a voltage of an output signal of the operational amplifier circuit to a predetermined voltage or below.Type: ApplicationFiled: December 11, 2017Publication date: April 12, 2018Applicant: OLYMPUS CORPORATIONInventors: Yasunari Harada, Masato Osawa, Hideki Kato
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Patent number: 9938459Abstract: An object of the present invention is to provide: an alkaline earth metal silicate phosphor to which Eu is added as an activator, and which has an emission peak wavelength of 600 nm or more, high luminance and excellent color rendering properties; and a method for producing the alkaline earth metal silicate phosphor. An alkaline earth metal silicate phosphor of the present invention is represented by composition formula (1) and having an emission peak wavelength of 600 nm or more and a circularity of 85% or more. Composition formula (1): (SraCabBacEud)2SieOf (in the formula, a, b, c, d, e and f satisfy 0.4<a<0.6, 0.4<b<0.6, 0.01<c<0.05, 0.01?d<0.4,0.7?e?1.3, 3.0?f?5.0 and a+b+c+d=1).Type: GrantFiled: June 17, 2013Date of Patent: April 10, 2018Assignees: SUMITOMO METAL MINING CO., LTD, TOHOKU UNIVERSITYInventors: Tetsufumi Komukai, Jun Yokoyama, Masato Kakihana, Satoko Tezuka, Hideki Kato
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Publication number: 20180062595Abstract: In a semiconductor device, a first variable gain amplifier and a second variable gain amplifier constitute a switched capacitor type variable gain amplifier. A selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and a load circuit such that the first variable gain amplifier and the load circuit are connected to each other when an amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain.Type: ApplicationFiled: October 19, 2017Publication date: March 1, 2018Applicant: OLYMPUS CORPORATIONInventors: Masato Osawa, Yasunari Harada, Hideki Kato
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Publication number: 20180047771Abstract: A semiconductor device includes a pixel array, a plurality of column circuits, an amplifier, switch arrays of a first layer to an nth layer, and signal lines of the first layer to the nth layer. n is an integer of two or more. The switch array of an ith layer is disposed between the switch array of an (i+1)th layer and the amplifier. i is an integer of one or more and less than n. The signal line of the first layer is connected to the nth amplifier. The signal line of the nth layer is connected to the switch array of the nth layer. Each of the plurality of switches included in the switch array of the nth layer is connected to the column circuit.Type: ApplicationFiled: October 26, 2017Publication date: February 15, 2018Applicants: OLYMPUS CORPORATION, OLYMPUS CORPORATIONInventors: Hideki Kato, Yasunari Harada, Masato Osawa
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Patent number: 9888199Abstract: This solid-state imaging device includes a first substrate and a second substrate which have circuit elements constituting pixels disposed therein are electrically connected to each other. The pixels includes: a photoelectric conversion element disposed in the first substrate; an amplifier circuit that amplifies a signal generated in the photoelectric conversion element to output the amplified signal; a signal accumulation circuit which is disposed in the second substrate and accumulates the amplified signal which is output from the amplifier circuit; and an output circuit that outputs the amplified signal accumulated in the signal accumulation circuit from the pixel.Type: GrantFiled: January 15, 2016Date of Patent: February 6, 2018Assignee: OLYMPUS CORPORATIONInventors: Yuichi Gomi, Hideki Kato, Naofumi Sakaguchi, Naoto Fukuoka
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Patent number: D815196Type: GrantFiled: July 1, 2016Date of Patent: April 10, 2018Assignee: SEIKO EPSON CORPORATIONInventors: Yoshiyuki Tanaka, Hideki Kato, Kenji Oshima, Kohei Usuda, Matt Delegate, David Keech
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Patent number: D828442Type: GrantFiled: May 29, 2017Date of Patent: September 11, 2018Assignee: SEIKO EPSON CORPORATIONInventors: Tomoyuki Higuchi, Koji Kawai, Hideki Kato, Matt Delegate, Kazunori Takabayashi
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Patent number: D829276Type: GrantFiled: May 29, 2017Date of Patent: September 25, 2018Assignee: SEIKO EPSON CORPORATIONInventors: Tomoyuki Higuchi, Koji Kawai, Hideki Kato, Matt Delegate, Kazunori Takabayashi
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Patent number: D839342Type: GrantFiled: July 3, 2018Date of Patent: January 29, 2019Assignee: SEIKO EPSON CORPORATIONInventors: Tomoyuki Higuchi, Koji Kawai, Hideki Kato, Matt Delegate, Kazunori Takabayashi
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Patent number: D841085Type: GrantFiled: May 29, 2017Date of Patent: February 19, 2019Assignee: SEIKO EPSON CORPORATIONInventors: Tomoyuki Higuchi, Koji Kawai, Hideki Kato, Matt Delegate, Kazunori Takabayashi
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Patent number: D843444Type: GrantFiled: December 26, 2017Date of Patent: March 19, 2019Assignee: SEIKO EPSON CORPORATIONInventors: Yoshiyuki Tanaka, Hideki Kato, Kenji Oshima, Takao Oizumi, Matt Delegate, David Keech