Patents by Inventor Hideki Matsumura

Hideki Matsumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7278833
    Abstract: A hybrid compressor includes a first compression mechanism, which is driven by a first drive source, a second compression mechanism, which is driven by a second drive source, and a communication path communicating between a suction chamber of the first compression mechanism and a suction chamber of the second compression mechanism. The first compression mechanism may be adapted only to be driven by the first drive source and the second compression mechanism may be adapted only to be driven the second drive source. Therefore, the compression mechanisms are adapted to their respective drive sources.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: October 9, 2007
    Assignee: Sanden Corporation
    Inventors: Akiyoshi Higashiyama, Hideki Matsumura, Suguru Okazawa
  • Publication number: 20070186970
    Abstract: A solar cell (100) comprising a semiconductor solar cell substrate (66) having a light receiving surface formed on the first major surface and generating photovoltaic power based on the light impinging on the light receiving surface, wherein the light receiving surface of the semiconductor solar cell substrate (66) is coated with a light receiving surface side insulating film (61) composed of an inorganic insulating material where the cationic component principally comprising silicon, and the light receiving surface side insulating film (61) is a low hydrogen content inorganic insulating film containing less than 10 atm % of hydrogen. A solar cell having an insulating film exhibiting excellent passivation effect insusceptible to aging can thereby be provided.
    Type: Application
    Filed: March 29, 2004
    Publication date: August 16, 2007
    Inventors: Masatoshi Takahashi, Hiroyuki Ohtsuka, Hideki Matsumura, Atsushi Masuda, Akira Izumi
  • Patent number: 7211152
    Abstract: A heating element CVD system wherein one or a plurality of connection terminal holders is placed in the processing container, and each of the connection terminal holders holds a plurality of connection terminals. Each of the connection terminals connects the heating element to the electric power supply mechanism electrically such that a connection region of the heating element connected to the connection terminal is not exposed to a space in the processing container.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 1, 2007
    Assignee: Anelva Corporation
    Inventors: Keiji Ishibashi, Masahiko Tanaka, Minoru Karasawa, Hideki Sunayama, Kazutaka Yamada, Hideki Matsumura, Atsushi Masuda
  • Publication number: 20070062648
    Abstract: A difficulty has been given, that is, in a condition that an electrostatic chuck having an oxide layer as a dielectric layer is set in catalytic chemical vapor deposition apparatus, as a silicon thin film is repeatedly deposited on a workpiece held by the electrostatic chuck, adsorbing power of the electrostatic chuck is gradually decreased, and finally the chuck does not adsorb a substrate at all. Thus, a dielectric layer on a surface of the electrostatic chuck is covered with an insulating film containing silicon nitride or silicon oxide. Thus, since damage to a chuck surface can be prevented, the damage being due to hydrogen radicals generated during depositing the silicon film by the catalytic chemical vapor deposition apparatus, even if the silicon film is repeatedly deposited, power for adsorbing the substrate is not decreased, and consequently substrate temperature is stabilized during depositing the silicon film.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 22, 2007
    Inventors: Shigeru Senbonmatsu, Shuhei Yamamoto, Mitsuru Suginoya, Hideki Matsumura, Atsushi Masuda
  • Publication number: 20070048200
    Abstract: A gas phase reaction processing device 25 comprising a processing chamber 14 into which reactive gas is introduced, substrate material 3 to be processed which is disposed within the processing chamber 14, a catalytic body 9 for decomposing the reactive gas introduced into the processing chamber 14, an electric power unit 10 for supplying power to the catalytic body 9, and an electrode structure 15 containing the catalytic body 9, the gas phase reaction processing device being characterized in that the electrode structure 15 is provided with a plurality of catalytic bodies 9 which are arranged substantially parallel with one another, a first group of terminals 7 and a second group of terminals 8 which are disposed opposite to sandwich this catalytic body 9 therebetween, wherein the first group of terminals 7 supports one end of the catalytic body 9 and the second group of terminals 8 supports the other end of the catalytic body 9 respectively, and a terminal block 6 adapted to support and electrically insulate
    Type: Application
    Filed: August 29, 2006
    Publication date: March 1, 2007
    Applicant: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Kazuhisa Takao, Hiroshi Ikeda, Hideki Matsumura, Atsushi Masuda, Hironobu Umemoto
  • Patent number: 7142236
    Abstract: A digital zoom apparatus includes an SDRAM. The SDRAM is stored with YUV data so that horizontal 4 pixels are assigned to each of addresses. A zoom start pixel is specified by a CPU on the basis of a zoom magnification. A memory control circuit transfers two lines of YUV data to a line memory with reference to an address to which the zoom start pixel is assigned, and furthermore, transfers part of the YUV data to a register. The line memory and the register are stored with the YUV data so that one pixel is assigned to each of addresses. The YUV data held in the register is subject to a zoom process with reference to the zoom start pixel, whereby, a through image subjected to an enlargement zooming process is displayed on a display.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: November 28, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Hideki Matsumura
  • Publication number: 20060055864
    Abstract: There is provided a method for selectively transferring pixel control devices onto a planar display substrate, which method enables prepared pixel control devices to be easily, reliably and inexpensively mounted without inducing any loss of pixel control devices. The pixel control devices (1) are formed in a large number at pitches (5, 6) obtained respectively by dividing pitches (105, 106) on the planar display substrate (100) by natural numbers. The pixel control devices corresponding to the number of the pitches (105, 106) on the planar display substrate (100) are picked up, retained on a transparent thermoplastic resin film (101) formed on the planar display substrate (100) utilizing the plastic deformation of the film and fixed at the peripheries thereof with a transparent ultraviolet curing resin film (104).
    Type: Application
    Filed: November 19, 2003
    Publication date: March 16, 2006
    Applicant: ISHIKAWA SEISAKUSHO, LTD.
    Inventors: Hideki Matsumura, Kenichiro Kida, Shigehira Minami
  • Publication number: 20060009017
    Abstract: Conventional methods of crystallizing a semiconductor film through scanning with a pulse laser have had a problem in that variation in particle diameter or shape of a crystal grain causes variation in characteristics of a thin film transistor, which lowers display quality of a liquid crystal display. In view of this, in a method of crystallizing a semiconductor film according to the present invention, after a step of performing scanning with a first pulse laser, scanning with a second pulse laser, which has a higher energy density than that of the first pulse laser, is performed in a substantially orthogonal direction to a traveling direction of scanning with the first pulse laser. With this method, the semiconductor film can be crystallized uniformly.
    Type: Application
    Filed: June 17, 2005
    Publication date: January 12, 2006
    Inventors: Shigeru Sembommatsu, Shuhei Yamamoto, Mitsuru Suginoya, Hideki Matsumura, Atsushi Masuda
  • Patent number: 6762792
    Abstract: A digital still camera includes a DRAM so that the DRAM is stored with pixel data having a Y, U or V component. A memory control circuit reads the pixel data out of the DRAM at a clock rate of 30 MHz, and writes it to SRAM. The memory control circuit then reads out the pixel data, that has been written from the SRAM to a first register, at a clock rate of 15 MHz and at a desired zoom magnification. An H/V interpolating circuit performs vertical interpolation and horizontal interpolation based on the data read out, and creates a zoom pixel. Since two pixels in a vertical direction is required to create one zoom pixel, the SRAM is formed with 2 lines of a memory area. Also, since only 1 line of data can read out of the DRAM at one time, the memory control circuit reads out the pixel data at a clock rate 2 times the value 15 MHz, i.e. 30 MHz.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: July 13, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Hideki Matsumura
  • Patent number: 6723664
    Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: April 20, 2004
    Assignees: NEC Compound Semiconductor Devices, Ltd., Anelva Corporation
    Inventors: Hideki Matsumura, Akira Izumi, Atsushi Masuda, Yasunobu Nashimoto, Yosuke Miyoshi, Shuji Nomura, Kazuo Sakurai, Shouichi Aoshima
  • Publication number: 20040065260
    Abstract: A heating element CVD system wherein one or a plurality of connection terminal holders is placed in the processing container, and each of the connection terminal holders holds a plurality of connection terminals. Each of the connection terminals connects the heating element to the electric power supply mechanism electrically such that a connection region of the heating element connected to the connection terminal is not exposed to a space in the processing container.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 8, 2004
    Applicants: ANELVA Corporation, JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Keiji Ishibashi, Masahiko Tanaka, Minoru Karasawa, Hideki Sunayama, Kazutaka Yamada, Hideki Matsumura, Atsushi Masuda
  • Patent number: 6717612
    Abstract: An integrated data detecting circuit 14 integrates digital data for each of detecting blocks set within a movement detecting area. A tripod-head control circuit 16 detects a correlation value for this integrated data to previously-registered integrated data, and compares the correlation value with a threshold to determine a first detecting block corresponding to an object. The tripod-head control circuit 16 further determines a first detecting area including the most first detecting blocks among a plurality of detecting areas set in the movement detecting area, and supplies to a drive device 18 a tripod-head control signal corresponding to the position. Accordingly, the drive device 18 controls a tripod head 20 such that a camera 12 is shifted in position to a direction of the first detecting area. Since determination is made for a first detecting area including the most first detecting blocks, the camera can be stabilized when an object is moving finely.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: April 6, 2004
    Assignee: Sanyo Electric Co., LTD
    Inventor: Hideki Matsumura
  • Patent number: 6703254
    Abstract: A semiconductor thin film including a well layer is laminated on a semiconductor substrate, the semiconductor substrate and the semiconductor thin film is cleaved, and a cleavage plane of the semiconductor substrate and the semiconductor thin film, which is obtained by the cleaving, is exposed to an atmosphere produced by decomposition of a gas containing N-atoms under the presence of a heated catalytic substance, thereby a surface layer of the cleavage plane is removed and a nitride layer is formed on the surface. Subsequently, a dielectric film is formed on the cleavage plane. According to the above technique, a natural oxide film formed on the cleavage plane can be removed and also a protective film can be formed by using a catalytic CVD apparatus.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: March 9, 2004
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Kimihiko Saitoh, Akira Izumi, Hideki Matsumura
  • Publication number: 20030152467
    Abstract: A hybrid compressor includes a first compression mechanism, which is driven by a first drive source, a second compression mechanism, which is driven by a second drive source, and a communication path communicating between a suction chamber of the first compression mechanism and a suction chamber of the second compression mechanism. The first compression mechanism may be adapted only to be driven by the first drive source and the second compression mechanism may be adapted only to be driven the second drive source. Therefore, the compression mechanisms are adapted to their respective drive sources.
    Type: Application
    Filed: February 3, 2003
    Publication date: August 14, 2003
    Inventors: Akiyoshi Higashiyama, Hideki Matsumura, Suguru Okazawa
  • Patent number: 6593548
    Abstract: A heating element CVD device capable of providing a high productivity and decomposing and/or activating the material gas led into a processing container by a heating element and stacking film on a substrate disposed in the processing container, wherein the connection part area of the heating element to a connection terminal for connecting the hearing element to a power supply mechanism is not exposed to a space inside the processing container, specifically, the connection part area is covered by a cylindrical body or a platy body covering the connection part area while providing a space part thereof from the hearing element, or the connection part area allows the space part to be present in a space thereof from the connection terminal and is covered by the cylindrical body or platy body covering the connection part area while providing the space part in a space thereof from the heating element, and hydrogen gas is led from the connection terminal side into the processing container through the space part, wher
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: July 15, 2003
    Assignees: Japan as represented by President of Japan Advanced Institute of Science and Technology, Anelva Corporation
    Inventors: Hideki Matsumura, Atsushi Masuda, Keiji Ishibashi, Masahiko Tanaka, Minoru Karasawa
  • Publication number: 20020189545
    Abstract: A heating element CVD device capable of providing a high productivity and decomposing and/or activating the material gas led into a processing container by a heating element and stacking film on a substrate disposed in the processing container, wherein the connection part area of the heating element to a connection terminal for connecting the hearing element to a power supply mechanism is not exposed to a space inside the processing container, specifically, the connection part area is covered by a cylindrical body or a platy body covering the connection part area while providing a space part thereof from the hearing element, or the connection part area allows the space part to be present in a space thereof from the connection terminal and is covered by the cylindrical body or platy body covering the connection part area while providing the space part in a space thereof from the heating element, and hydrogen gas is led from the connection terminal side into the processing container through the space part, wher
    Type: Application
    Filed: May 14, 2002
    Publication date: December 19, 2002
    Inventors: Hideki Matsumura, Atsushi Matsuda, Keiji Ishibashi, Masahiko Tanaka, Minoru Karasawa
  • Publication number: 20020155631
    Abstract: A semiconductor thin film including a well layer is laminated on a semiconductor substrate, the semiconductor substrate and the semiconductor thin film is cleaved, and a cleavage plane of the semiconductor substrate and the semiconductor thin film, which is obtained by the cleaving, is exposed to an atmosphere produced by decomposition of a gas containing N-atoms under the presence of a heated catalytic substance, thereby a surface layer of the cleavage plane is removed and a nitride layer is formed on the surface. Subsequently, a dielectric film is formed on the cleavage plane.
    Type: Application
    Filed: April 22, 2002
    Publication date: October 24, 2002
    Inventors: Kimihiko Saitoh, Akira Izumi, Hideki Matsumura
  • Publication number: 20020154228
    Abstract: A digital zoom apparatus includes an SDRAM. The SDRAM is stored with YUV data so that horizontal 4 pixels are assigned to each of addresses. A zoom start pixel is specified by a CPU on the basis of a zoom magnification. A memory control circuit transfers two lines of YUV data to a line memory with reference to an address to which the zoom start pixel is assigned, and furthermore, transfers part of the YUV data to a register. The line memory and the register are stored with the YUV data so that one pixel is assigned to each of addresses. The YUV data held in the register is subject to a zoom process with reference to the zoom start pixel, whereby, a through image subjected to an enlargement zooming process is displayed on a display.
    Type: Application
    Filed: April 18, 2002
    Publication date: October 24, 2002
    Applicant: Sanyo Electric Co., Ltd.
    Inventor: Hideki Matsumura
  • Publication number: 20020086557
    Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
    Type: Application
    Filed: January 10, 2002
    Publication date: July 4, 2002
    Inventors: Hideki Matsumura, Akira Izumi, Atsushi Masuda, Yasunobu Nashimoto, Yosuke Miyoshi, Shuji Nomura, Kazuo Sakurai, Shouichi Aoshima
  • Patent number: 6349669
    Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV−1 cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: February 26, 2002
    Assignees: NEC Corporation, Anelva Corporation
    Inventors: Hideki Matsumura, Akira Izumi, Atsushi Masuda, Yasunobu Nashimoto, Yosuke Miyoshi, Shuji Nomura, Kazuo Sakurai, Shouichi Aoshima