Abstract: A method of cleaning an evaporator of an ice maker can include activating a switch of the ice maker in a first manual intervention of an overall cleaning procedure to initiate the overall cleaning procedure; sounding an audible alarm to alert a user that a second manual intervention is required; pouring a cleaning fluid into a tank of the evaporator case in the second manual intervention; automatically initiating and completing one of a cleaning stage and a sanitizing stage upon completion of the second manual intervention, automatically initiating the one of the cleaning stage and the sanitizing stage including operating a cleaning valve of a water circuit of the ice maker by a main controller of the ice maker; and automatically initiating and completing a rinsing stage.

Abstract: An ice machine includes: an ice maker including: an ultrasonic bin sensor mounted to a body; and a controller in electrical communication with the ultrasonic bin sensor and configured to control the ultrasonic bin sensor; and a storage bin coupled to the ice maker and sized to receive a mound of ice, a lens of the ultrasonic bin sensor facing a bottom of an interior cavity of the storage bin, the controller configured to process a return signal of the ultrasonic bin sensor to control a level of ice stored inside the storage bin, the controller further configured to apply a predetermined time delay to filter out a portion of the return signal that exceeds a threshold voltage but does not exceed the time delay.

Abstract: An ice maker includes a dry compartment and a wet compartment adjacent to the dry compartment and including: an evaporator case sized to receive an evaporator, the evaporator case including: a plurality of interior panels joined to each other with snap-fit joints, each of the snap-fit joints including a tab and defining a slot, each of a plurality of seams formed between the interior panels defining a foam-tight seal and a water-tight seal; and a plurality of exterior panels, each of the plurality of exterior panels joined to a mating interior panel of the plurality of interior panels with slide joints, wherein the evaporator case is integrally insulated with blown foam insulation positioned between each of the plurality of exterior panels and a corresponding interior panel.

Abstract: An ice machine includes: an ice maker including: an ultrasonic bin sensor mounted to a body; and a controller in electrical communication with the ultrasonic bin sensor and configured to control the ultrasonic bin sensor; and a storage bin coupled to the ice maker and sized to receive a mound of ice, a lens of the ultrasonic bin sensor facing a bottom of an interior cavity of the storage bin, the controller configured to process a return signal of the ultrasonic bin sensor to control a level of ice stored inside the storage bin, the controller further configured to apply a predetermined time delay to filter out a portion of the return signal that exceeds a threshold voltage but does not exceed the time delay.

Abstract: A method of cleaning an evaporator of an ice maker can include activating a switch of the ice maker in a first manual intervention of an overall cleaning procedure to initiate the overall cleaning procedure; sounding an audible alarm to alert a user that a second manual intervention is required; pouring a cleaning fluid into a tank of the evaporator case in the second manual intervention; automatically initiating and completing one of a cleaning stage and a sanitizing stage upon completion of the second manual intervention, automatically initiating the one of the cleaning stage and the sanitizing stage including operating a cleaning valve of a water circuit of the ice maker by a main controller of the ice maker; and automatically initiating and completing a rinsing stage.

Abstract: An ice machine includes: an ice maker including: an ultrasonic bin sensor mounted to a body; and a controller in electrical communication with the ultrasonic bin sensor and configured to control the ultrasonic bin sensor; and a storage bin coupled to the ice maker and sized to receive a mound of ice, a lens of the ultrasonic bin sensor facing a bottom of an interior cavity of the storage bin, the controller configured to process a return signal of the ultrasonic bin sensor to control a level of ice stored inside the storage bin, the controller further configured to apply a predetermined time delay to filter out a portion of the return signal that exceeds a threshold voltage but does not exceed the time delay.

Abstract: An ice maker includes a dry compartment and a wet compartment adjacent to the dry compartment and including: an evaporator case sized to receive an evaporator, the evaporator case including: a plurality of interior panels joined to each other with snap-fit joints, each of the snap-fit joints including a tab and defining a slot, each of a plurality of seams formed between the interior panels defining a foam-tight seal and a water-tight seal; and a plurality of exterior panels, each of the plurality of exterior panels joined to a mating interior panel of the plurality of interior panels with slide joints, wherein the evaporator case is integrally insulated with blown foam insulation positioned between each of the plurality of exterior panels and a corresponding interior panel.

Abstract: An ice machine includes: an ice maker including: an ultrasonic bin sensor mounted to a body; and a controller in electrical communication with the ultrasonic bin sensor and configured to control the ultrasonic bin sensor; and a storage bin coupled to the ice maker and sized to receive a mound of ice, a lens of the ultrasonic bin sensor facing a bottom of an interior cavity of the storage bin, the controller configured to process a return signal of the ultrasonic bin sensor to control a level of ice stored inside the storage bin, the controller further configured to apply a predetermined time delay to filter out a portion of the return signal that exceeds a threshold voltage but does not exceed the time delay.

Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).

Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).

Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).

Abstract: The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal. A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.

Abstract: The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal.

Abstract: Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

Abstract: Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

Abstract: Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

Abstract: The throughput of external output actions of read data from memory blocks that are capable of parallel operation is improved.

Abstract: A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.