Abstract: A data processor is composed of a register file including a plurality of registers each of which stores therein an operand data, a register pointer section which includes a plurality of register pointers, an instruction register, a data type converter unit, and a processing unit. Each of the register pointers stores therein a register address and a data type of the operand data stored in the register specified by the register address. The instruction register fetches an instruction word including an operation code, and an operand field. The operand field is representative of a register pointer address used for addressing a selected one of the register pointers to thereby indirectly addressing a selected one of the register.

Abstract: The invention provides a liquid crystal projector which can blast an increased amount of cooling air to raise the cooling efficiency without increasing the size of an optical prism unit. The liquid crystal projector includes a dichroic prism, a base for securing the dichroic prism with a lower plate interposed therebetween, a plurality of liquid crystal panel units disposed on side faces of the dichroic prism, and a cooling fan disposed below the base. The base has air holes formed therein such that air current generated by the cooling fan is introduced to the liquid crystal panel units through the air holes to cool the liquid crystal panel units. The lower plate has inclined faces at portions thereof which oppose to the air holes of the base.

Abstract: The invention provides a liquid crystal projector which can blast an increased amount of cooling air to raise the cooling efficiency without increasing the size of an optical prism unit. The liquid crystal projector includes a dichroic prism, a base for securing the dichroic prism with a lower plate interposed therebetween, a plurality of liquid crystal panel units disposed on side faces of the dichroic prism, and a cooling fan disposed below the base. The base has air holes formed therein such that air current generated by the cooling fan is introduced to the liquid crystal panel units through the air holes to cool the liquid crystal panel units. The lower plate has inclined faces at portions thereof which oppose to the air holes of the base.

Abstract: A data processor is composed of a register file including a plurality of registers each of which stores therein an operand data, a register pointer section which includes a plurality of register pointers, an instruction register, a data type converter unit, and a processing unit. Each of the register pointers stores therein a register address and a data type of the operand data stored in the register specified by the register address. The instruction register fetches an instruction word including an operation code, and an operand field. The operand field is representative of a register pointer address used for addressing a selected one of the register pointers to thereby indirectly addressing a selected one of the registers. The data type converter unit executes a data conversion on the operand data stored in the selected one of the registers to produce a converted operand data, on the basis of the data type stored in the selected register pointer specified by the register pointer address.

Abstract: A super scalar processor includes execution units for data processing on integers, an execution unit for multiplication, an execution unit for data loading/storing and an electric power and clock controller for supplying electric power and a clock signal to them, and one of the execution units for data processing on integers includes an emulator for emulating instruction codes to be executed by the execution unit for multiplication to instruction codes thereto; while the execution unit for multiplication is powered down or off, an instruction analyzing and distributing unit changes the issuance of the instruction codes to the execution unit, and the instruction codes are emulated so as to achieve the given jobs; when an instruction code makes the execution unit for multiplication recovered from the idling state, the execution unit becomes enable after a time lug automatically given thereto so that the super scalar processor is improved in operability.

Abstract: The VLIW processor according to the present invention, which executes in parallel a plurality of processings described in parallel in a VLIW instruction using a plurality of execution pipelines, performs pipeline execution of processings selected and designated from among the plurality of processings based on the VLIW instruction in respective steps on a diagonal formed by shifting one step at a time starting with an initial step in the order of parallel arrangement of the plurality of execution pipelines, one by one in the direction of the diagonal.

Abstract: A play device for generating a synthesized self-portrait which includes a photographed image of a player and frame is disclosed in the present invention. The device includes a terminal for displaying and printing the synthesized self-portrait, a network server for providing the self-portrait data of each player assigned to ID code data at designated terminals, a management device for managing the play device, and a monitoring system for monitoring various operation conditions of the play device.

Abstract: A play device for generating a synthesized self-portrait having a photographed image of a player and a frame image, the device including a terminal for displaying and printing the synthesized self-portrait, a network server for providing a commercial data to be shown on the terminal while the player waits for printing of the synthesized self-portrait, the commercial data being renewed in the terminal without interfering with generation of the synthesized self-portrait, a management device for managing the play device, and a monitoring system for monitoring various operating conditions of the play device.

Abstract: A data processor has an internal data bus and an instruction fetch bus provided separately from each other. When a data-read operation mode is designated, data stored in an internal read only memory are read out onto both the internal data bus and the instruction fetch bus, and the data on these buses are then subject to an operation by an execution unit to check the coincidence therebetween, the comparison resultant signal being transferred to the outside.

Abstract: A data processing apparatus executing in a pipelined manner a plurality of instruction including first and second instructions, the first instruction having first register address information and the second instruction having a second register address information, the data processing apparatus has a register file 110 including a plurality of registers, execution means 117, 118 for receiving and executing the first instruction to produce memory address information in a first pipeline cycle and for receiving and executing the second instruction to produce processed data, which is to be stored in the register file 110, in a second pipeline cycle succeeding to the first pipeline cycle, a memory circuit including a data memory 124 and an access control circuit reading out memory data, which is to be stored in the register file, from a memory area of the data memory 124 designated by the memory address information in the second pipeline cycle, and control means 133 for allowing the processed data to be stored in th

Abstract: In a CPU comprising a CPU section and a BCU section, the processing speed of the CPU section is prevented from decreasing, the amount of power consumed by the CPU section is reduced, and the need of a wait control function in the CPU section is eliminated. A clock control section 105c distributes an externally supplied clock 111 to the inside of a CPU section 101 and a BCU section 105. During a read access request from the CPU section 101 to a storage device 106, the period of a CPU clock 112 supplied to the CPU section 101 is extended. That is, the state immediately before the change point of the CPU clock 112 when the CPU section 101 inputs input data via an internal data bus 104 is extended until read data has been established on the internal data bus 104.

Abstract: A data processor has an internal data bus and an instruction fetch bus provided separately from each other. When a data-read operation mode is designated, data stored in an internal read only memory are read out onto both the internal data bus and the instruction fetch bus, and the data on these buses are then subject to an operation by an execution unit to check the coincidence therebetween, the comparison resultant signal being transferred to the outside.