Abstract: A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between activating and deactivating states of the first inverter, the first clock signal-synchronized inverter having a first input connected to a corresponding one of the bit lines and a first output. A second clock signal-synchronized inverter is arranged in parallel with the first clock signal-synchronized inverter and includes a second inverter and a second switch for switching between activating and deactivating states of the second inverter, the second clock signal-synchronized inverter having an input connected to the output of the first clock signal-synchronized inverter and an output connected to the input of the first clock signal-synchronized inverter.

Abstract: A plurality of electrically erasable programmable read-only memories or EEPROMs are associated with a controller LSI. Each EEPROM includes an array of floating-gate tunneling memory cell transistors arranged in rows and columns. When a sub-array of memory cell transistors providing a one-page data is selected for programming, the controller LSI performs a write/verify operation as follows the electrically written state after the programming of the selected memory cell transistors is verified by checking their threshold values for variations, and when any potentially insufficient cell transistor remains among them, the rewrite operation using a predetermined write voltage for a predetermined period of time is repeated so that the resultant write state may come closer to a satisfiable reference state. Each rewrite/verify operation is performed by applying the write voltage to the insufficient cell transistor for a predetermined period of time.

Abstract: A semiconductor integrated circuit includes a MOS transistor, and a transistor circuit in which one end of a current path is connected to a drain of this MOS transistor and which has an avalanche breakdown voltage lower than a breakdown voltage of the MOS transistor.