Patents by Inventor Hideki Tsuya

Hideki Tsuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8486772
    Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: July 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideki Tsuya, Masaharu Nagai
  • Patent number: 8367517
    Abstract: An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideki Tsuya, Yoshihiro Komatsu
  • Publication number: 20130023108
    Abstract: An insulating layer is formed on a surface of a semiconductor wafer which is to be a bond substrate and an embrittlement region is formed in the semiconductor wafer by irradiation with accelerated ions. Then, a base substrate and the semiconductor wafer are attached to each other. After that, the semiconductor wafer is divided at the embrittlement region by performing heat treatment and an SOI substrate including a semiconductor layer over the base substrate with the insulating layer interposed therebetween is formed. Before the SOI substrate is formed, heat treatment is performed on the semiconductor wafer at a temperature of higher than or equal to 1100° C. under a non-oxidizing atmosphere in which the concentration of impurities is reduced. In this manner, the planarity of the film formed on the semiconductor wafer when heat treatment is performed can be improved.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 24, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Yujiro SAKURADA, Hideki TSUYA, Makoto FURUNO, Miku FUJITA
  • Publication number: 20120208348
    Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Hideki TSUYA, Masaharu NAGAI
  • Patent number: 8168481
    Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: May 1, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideki Tsuya, Masaharu Nagai
  • Publication number: 20110183445
    Abstract: An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 28, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Hideki TSUYA, Yoshihiro KOMATSU
  • Publication number: 20100273310
    Abstract: The method of one embodiment of the present invention includes: a first step of irradiating a bond substrate with ions to form an embrittlement region in the bond substrate; a second step of bonding the bond substrate to a base substrate with an insulating layer therebetween; a third step of splitting the bond substrate at the embrittlement region to form a semiconductor layer over the base substrate with the insulating layer therebetween; and a fourth step of subjecting the bond substrate split at the embrittlement region to a first heat treatment in an argon atmosphere and then a second heat treatment in an atmosphere of a mixture of oxygen and nitrogen to form a reprocessed bond substrate. The reprocessed bond substrate is used again as a bond substrate in the first step.
    Type: Application
    Filed: April 19, 2010
    Publication date: October 28, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Hideki TSUYA, Masaharu NAGAI
  • Patent number: 7360964
    Abstract: A joint structure is for joining a pair of connecting members to each other. One of the connecting members has a lock portion formed so as to protrude from the member, and the other connecting member is provided with a receiving portion into which the lock portion is insertable. The lock portion is inserted into the receiving portion while at least one of the lock and receiving portions is being resiliently flexed. Thereafter, the lock or receiving portion is restored to its initial shape. As a result, the lock and receiving portions are joined to each other. The lock and receiving portions are abutted against each other such that at least one of the lock and receiving portions deforms the other into engagement with one another. As a result, this deformation limits relative movement between the lock and receiving portions.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: April 22, 2008
    Assignee: Araco Kabushiki Kaisha
    Inventors: Hideki Tsuya, Naoki Hirose
  • Patent number: 7126194
    Abstract: On a silicon layer of an SOI wafer is defined a semiconductor device-forming region to form semiconductor devices thereon and an insulating region to electrically insulate the semiconductor device-forming region. Then, a mask layer is formed of nitride by means of photolithography so as to cover the semiconductor device-forming region. Then, an impurities-removing layer is formed by means of well known technique so as to cover the mask layer and embed the gaps between the adjacent masks of the mask layer. The impurities of the silicon layer of the SOI wafer are absorbed and removed by the distorted layer, the grain boundaries and the lattice defects of the impurities-removing layer.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: October 24, 2006
    Assignees: Hyogo Prefecture, Japan Society for the Promotion of Science
    Inventors: Seigo Kishino, Hideki Tsuya
  • Publication number: 20050054229
    Abstract: A joint structure for joining a pair of connecting members to each other is disclosed. One of the connecting members has a lock portion formed so as to protrude from the member and the other connecting member is provided with a receiving portion into which the lock portion is insertable. The lock portion is inserted into the receiving portion while at least one of the lock and receiving portions is being resiliently flexed. Thereafter, the lock or receiving portion is restored to their initial shape. As a result, the lock and receiving portions are joined to each other. The lock and receiving portions are abutted against each other such that at least one of the lock and receiving portions deforms the other into engagement with one another. As a result, the deformation limits the relative movement between the lock and receiving portions.
    Type: Application
    Filed: September 1, 2004
    Publication date: March 10, 2005
    Inventors: Hideki Tsuya, Naoki Hirose
  • Publication number: 20040150087
    Abstract: On a silicon layer of an SOI wafer is defined a semiconductor device-forming region to form semiconductor devices thereon and an insulating region to electrically insulate the semiconductor device-forming region. Then, a mask layer is formed of nitride by means of photolithography so as to cover the semiconductor device-forming region. Then, an impurities-removing layer is formed by means of well known technique so as to cover the mask layer and embed the gaps between the adjacent masks of the mask layer. The impurities of the silicon layer of the SOI wafer are absorbed and removed by the distorted layer, the grain boundaries and the lattice defects of the impurities-removing layer.
    Type: Application
    Filed: November 10, 2003
    Publication date: August 5, 2004
    Applicants: HYOGO PREFECTURE, JAPAN SOCIETY FOR THE PROMOTION OF SCIENCE
    Inventors: Seigo Kishino, Hideki Tsuya