Abstract: This invention provides a thermal transfer sheet causing little static electricity during transfer onto a material as a transfer image support, and printed matter excellent in antistatic properties. The thermal transfer sheet comprises a protective transfer layer provided in at least part of one surface of a base sheet via a nontransferable release layer so as to be peelable, and has an antistatic agent contained in at least one of the release layer and the protective transfer layer. Printed matter is prepared by transferring the protective transfer layer from the above thermal transfer sheet onto an image formed on a substrate by a sublimation transfer process so as to cover at least part of the image.

Abstract: A protect layer transfer sheet of the present invention comprises a substrate, an untransferable release layer and a thermally transferable protect layer, the protect layer being disposed on at least one area of a surface of the substrate by the medium of the release layer. The release layer contains at least one substance selected from the group consisting of inorganic particles having a mean particle size of 40 nm or less, alkyl vinyl ether--maleic anhydride copolymer, derivatives of the alkyl vinyl ether--maleic anhydride copolymer and ionomer. According to the present invention, it is possible that a protect layer is surely and constantly transferred on an image formed in a printed product at all times. Furthermore it is also possible to make the thermally transferable protect layer a single-ply structure by omitting an adhesive layer. The single-ply structure of the protect layer has an improved transparency, thus increasing the highest density of a highly quality image covered with the protect layer.

Abstract: An input signal SIN is input to a reset input terminal R of a flip-flop RSFF1 and, at the same time, input to a gate of a pMOS transistor MP1 constituting a transfer control circuit DCNTL1, a signal Bd obtained by delaying an inverted output signal B of the flip-flop RSFF1 at a delay circuit DLY1 is input to the data input terminal of the transfer control circuit DCNTL1, and the output signal of the transfer control circuit DCNTL1 is input to a set input terminal S of the flip-flop RSFF1 via two stages of inverters connected in series, therefore, a signal change detection circuit capable of generating a stable pulse according to the level change of the input signal without depending upon the input clock signal and capable of generating the pulse at high speed can be realized.

Abstract: A voltage level shifting circuit which enables realization of high sensitivity input, high speed, and large output amplitude with a low power consumption, wherein a flipflop is constituted by two CMOS inverters, INV.sub.1 and INV.sub.2, the power voltage sides of the CMOS inverters are used as the inputs of the signals, transfer gates are connected between the input terminals of the input signals and the input terminals of the CMOS inverters, and the transfer gates are turned on and off by the same clock signal CLK.

Abstract: The memory ratio is improved and the data holding ability on reading data is enhanced by providing a resistive element between an access transistor and a flip-flop, which form a memory cell of a static memory. Even if the threshold voltage of the access transistor is lowered, the memory cell ratio can be increased. Accordingly, the minimum operating voltage can be lowered and the operating margin for a power source voltage can be increased and simultaneously with this, the soft error immunity can be enhanced. Since the memory cell ratio of the semiconductor memory of the present invention is enhanced by the resistive element, the necessity to preset a lower current drive ability of the access transistor for a drive transistor is decreased. As a result of this, the size of the memory cell can be decreased. Further, the current consumed by the memory cell is decreased by the resistive element.

Abstract: A voltage level shifter circuit includes a pair of CMOS invertors having inputs and outputs cross connected thereto. One of a pair of power source terminals of each of the CMOS invertors is grounded, and complementary input signals are supplied to the CMOS invertors by way of the other power source terminals, and output signals are taken out from output terminals of the CMOS invertors. The voltage level shifter circuit level shifts an input amplitude substantially equal to an input threshold value of transistors to the voltage level of the power source while suppressing the dc consumption current.

Abstract: A static random access memory (SRAM) includes a pair of p-channel metal-oxide-semiconductor (PMOS) transistors which serve as variable resistors for terminating bit lines and a control circuit for causing the PMOS transistors to have a low impedance level during read out and an intermediate impedance level during writing so that sudden d.c. current is suppressed and the voltage at the bit lines is prevented from being lowered. The variable resistor device can constitute a current mirror circuit along with a metal-insulator-semiconductor (MIS) transistor of the control circuit, so that it becomes possible to provide a stable control which is invulnerable to manufacturing tolerances.

Abstract: A delay circuit for integrated circuits includes a current mirror circuit having at least a pair of MIS transistors, a constant current source and a capacitance. The delay time is determined by the charging time of the capacitance connected to one of the MIS transistors. A stable delay time is obtained regardless of manufacturing variations and the space required for the circuit is reduced.