Abstract: Graphic data having a two-dimensional spread is divided into data blocks having a two-dimensional spread, for example, data blocks of 8.times.8 pixels, and with these data blocks as units, cache control is performed. A tag memory for making a decision as to the occurrence of a cache hit, stores therein a tag and a valid flag as well as a bank address in a cache memory at which the data block in question is stored. As a result, the relationship between each bank of the cache memory and the address in the tag memory is not fixed, which ensures efficient use of the cache memory even in situations where accesses concentrate in one particular memory area.

Abstract: A parallel computer includes a sequence of adjacent nodes, with each node including at least first and second processing elements and each processing element including a memory. The nodes are sequentially added or replaced in a node order and the processing elements are sequentially connected to form a single ring data path. First matrix data elements are sequentially assigned to adjacent processing elements along the single ring data path and second matrix data element groups are sequentially assigned to processing elements in the node order. The first matrix data elements are then accumulated with the second matrix data element groups as the first matrix data elements are rotated along the single ring data path. Accordingly, accumulation results are maintained within the memories of the lowest order nodes such that the nodes may added or replaced without relocation of data.

Abstract: A parallel data processing system uses a parallel learning method capable of having sufficient parallelness to shorten learning time and has plural data processing units, each connected to a data transfer unit and having a unit for holding execution parameters as are required for data processing, a unit for holding partial sample data which comprises at least part of the full sample data necessary for the required data processing, an adjustment value calculation unit which calculates, from partial sample data stored in the unit for holding partial sample data and from the execution parameters held in the execution parameter holding unit, adjustment amounts related to the execution parameters with regard to the partial sample data and, further, an accumulator which, when calculating the overall total of the execution parameter adjustment amounts with regard to the full sample data, accumulates the adjustment amounts related to the execution parameters with regard to the partial sample data at the data processi

Abstract: A parallel data processing system comprises a plurality of data processing units each having at least one input and storing data of a matrix and a plurality of trays each having a first input and an output and for storing data of a vector, each of all or part of said trays having a second output connected to said first input of a respective one of said data processing units, and said trays being connected in cascade to form a shift register for performing data transfer between corresponding ones of the trays and the data processing units and data processing in the data processing units synchronously, thereby performing an operation of a matrix vector product or a neuron computer operation on analog signals.

Abstract: A parallel data processing system processes data by synchronously operating a plurality of data processing units (processor elements). It aims at reducing the overhead caused by the data transmission in a system, performing a matrix operation and a neurocomputer operation by making the best of its parallel processing method, and at using excess units for another operation when the number of units required for an operation is smaller than the number of the existing units. The parallel data processing system comprises a plurality of data processing units; a plurality of trays which store and transmit data, each connected to a data processing unit; a tray connection switching unit for changing the connection state of the data transmission path between trays, dividing data processing units into a plurality of groups, and performing an independent operation on each group; and a clock generator for synchronously operating a data transmission between trays and a data process in a data processing unit.

Abstract: A parallel data processing system performs a data processing by using a plurality of data processing units, namely, processor elements, synchronously. The parallel data processing system comprises a plurality of data processing units, a plurality of trays, and a clock generator. The plurality of trays are connected to respective data processing units and have a function of storing a plurality of data and a function of transmitting the data. The clock generator is producing a clock so that the data transfer between the trays and between the trays and the data processing units, and the data processing in the data processing unit is executed synchronously. Data are transferred between trays during the period in which they are processed, thus substantially eliminating the data transmission time.

Abstract: An asynchronous control system for a neuro computer, includes an inter-connected type neural network composed of a plurality of neurons for multiplying a plurality of input signals with corresponding weights, calculating a total sum-of-products of the input signals and weight, thereby providing the sum-of product signals, and converting the sum-of-product signal using a non-linear function. A weight memory is provided for storing data of the weights for said neurons, and a controller is provided for generating a control pattern which controls the neural network. A selector randomly selects one of the neurons which performs signal processing during one processing cycle.

Abstract: A floating-point arithmetic system, which allows arithmetic operations, including at least addition and subtraction, to be performed for floating-point data. The system includes multiple-input addition and subtraction devices for executing adding and subtracting calculations of at least three floating-point data. Preferably, the multiple-input addition and subtraction devices includes a multiple-input device which enables at least three floating-point data to be input, a shift-amount determining device having a look up table which compares the respective exponents in parallel, selects the maximum exponent and determines the amount of shift in the respective mantissas; and a mantissa shifting devices, e.g., at least one multiplexer, which shifts the respective mantissas in accordance with the amount of shift and makes an adjustment of digit positions of the mantissas.

Abstract: An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.

Abstract: A parallel data processing apparatus including a plurality of processors, a pair of signal paths are provided for each processor, one signal path of each pair being used for supplying a predetermined signal to the processor, and the second signal path being used for returning the signal from the processor to a predetermined position common to all of the processors. Each of the above signal paths include a variable delay unit. The apparatus further includes a delay measuring unit for measuring the time elapsing while the signal is propagated from the above predetermined position to a corresponding processor and then returned from the processor to the above predetermined position through each pair of signal paths. Further the apparatus includes a delay adjusting unit for adjusting the delays caused by the variable delay units in all of the signal paths.

Abstract: An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors.

Abstract: A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.

Abstract: An analogue neuron processor (ANP) performs an operation of sum-of-products of a time divisional analog input signal sequentially input from an analog signal bus and weight data and output an analog signal to an analog signal bus through a nonlinear circuit. A layered type or a feedback type neural network is formed of ANPs. The neural network reads necessary control data from a control pattern memory under the control of micro sequencer and reads the necessary weight data from the weight memory thereby realizing a neuron computer. The neuron computer connects a plurality of ANPs by using a single analog bus, thereby greatly decreasing the number of the wires used for the neural network and also decreasing the size of the circuit. A plurality of ANPs in a single layer simultaneously receives analog signal from an analog bus and carries out a parallel operation in the same time period and ANPs in different layers perform a parallel operation in a pipeline manner, thereby increasing a speed of an operation.

Abstract: An improved implant comprising a metallic base material and a coating layer of a ceramics which is formed by thermally sprayed firstly a bonding agent and secondly ceramic powders (optionally containing a porcelain) around the outersurface of the metallic base material. The implant has a sufficient mechanical strength (e.g. impact strength) and hence an excellent break-resistance and further a good affinity to tissues of living bodies and is useful for implantation in various bones including tooth roots and joints in living bodies.