Patents by Inventor Hidemasa Takahashi

Hidemasa Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11930136
    Abstract: A reading device includes: plural transport rolls that transport a document along a transport path, include a discharge roll disposed on a most downstream side of the transport path, and rotate and do not rotate in synchronization with one another; an opening and closing unit that exposes or covers an upstream portion of the transport path; plural detectors that are provided apart from one another along the transport path, detect a transported document, and include a discharge detector that is disposed on a most downstream side of the transport path and is disposed on an upstream side relative to the discharge roll in a document transport direction; a reader that reads an image formed on a transported document in a downstream portion of the transport path; and a controller that stops the plural transport rolls once upon occurrence of a document jam inside a device body by controlling the transport rolls and rotates the transport rolls for only a predetermined period in a case where the discharge detector is d
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: March 12, 2024
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Noriyuki Obara, Hidemasa Takahashi, Kazunobu Sato, Shigeru Tamura, Yuki Iguchi
  • Publication number: 20230053917
    Abstract: A reading device includes: plural transport rolls that transport a document along a transport path, include a discharge roll disposed on a most downstream side of the transport path, and rotate and do not rotate in synchronization with one another; an opening and closing unit that exposes or covers an upstream portion of the transport path; plural detectors that are provided apart from one another along the transport path, detect a transported document, and include a discharge detector that is disposed on a most downstream side of the transport path and is disposed on an upstream side relative to the discharge roll in a document transport direction; a reader that reads an image formed on a transported document in a downstream portion of the transport path; and a controller that stops the plural transport rolls once upon occurrence of a document jam inside a device body by controlling the transport rolls and rotates the transport rolls for only a predetermined period in a case where the discharge detector is d
    Type: Application
    Filed: December 2, 2021
    Publication date: February 23, 2023
    Applicant: FUJIFILM BUSINESS INNOVATION CORP.
    Inventors: Noriyuki OBARA, Hidemasa TAKAHASHI, Kazunobu SATO, Shigeru TAMURA, Yuki IGUCHI
  • Patent number: 10958801
    Abstract: An image scanning apparatus includes: a reading unit that reads image data, which includes an image of a document transported along a transport path and an image at a scanning position of the image, from a storage area in synchronization with a reading synchronization signal; a detection unit that detects a dirt at the scanning position by processing the image data; and a delay unit that delays and outputs a period, during which the synchronization signal to be provided to the detection unit is valid, until reading of data of a document part included in the image data starts.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: March 23, 2021
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hidemasa Takahashi, Fumihito Kasai, Atsuhiro Itoh
  • Patent number: 10886695
    Abstract: Improve semiconductor device performance. The wiring WL1A on which the semiconductor chip CHP1 in which the semiconductor lasers LD is formed is mounted has a stub STB2 in the vicinity of the mounting area of the semiconductor chip CHP1.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: January 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuaki Tsuchiyama, Motoo Suwa, Hidemasa Takahashi
  • Publication number: 20200344374
    Abstract: An image scanning apparatus includes: a reading unit that reads image data, which includes an image of a document transported along a transport path and an image at a scanning position of the image, from a storage area in synchronization with a reading synchronization signal; a detection unit that detects a dirt at the scanning position by processing the image data; and a delay unit that delays and outputs a period, during which the synchronization signal to be provided to the detection unit is valid, until reading of data of a document part included in the image data starts.
    Type: Application
    Filed: October 28, 2019
    Publication date: October 29, 2020
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Hidemasa TAKAHASHI, Fumihito KASAI, Atsuhiro ITOH
  • Publication number: 20200083663
    Abstract: Improve semiconductor device performance. The wiring WL1A on which the semiconductor chip CHP1 in which the semiconductor lasers LD is formed is mounted has a stub STB2 in the vicinity of the mounting area of the semiconductor chip CHP1.
    Type: Application
    Filed: August 19, 2019
    Publication date: March 12, 2020
    Inventors: Kazuaki TSUCHIYAMA, Motoo SUWA, Hidemasa TAKAHASHI
  • Patent number: 6373081
    Abstract: A field effect transistor includes (a) a semi-insulating GaAs substrate, (b) a step-doped structured active layer including an n type GaAs layer deposited on the substrate, and an n− type GaAs layer or a non-doped GaAs layer deposited on the n type GaAs layer, the n− type GaAs layer or non-doped GaAs layer being formed with at least one recess, and (c) a gate electrode formed in the recess so that the gate electrode is oriented in such a direction that drain current runs in the active layer along crystal orientation [01(−1)]. The field effect transistor enhances linearity of transfer conductance, and further improves strain characteristic.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventors: Junko Morikawa, Hidemasa Takahashi, Kazunori Asano
  • Patent number: 6033942
    Abstract: A comb-shape MESFET assembly has a plurality of unit FETs including first, second and third groups of unit FETs. The pinch-off voltages of the unit FETs are different from group to group by a step difference. The different pinch-off voltages provide a tailored change in the third-order intermodulation distortion in the output of the MESFET assembly. The step difference in the pinch-off voltage is generated by different thicknesses or impurity concentrations of a semiconductor active layer, different gate length of the unit FETs or different types of stress in the gate insulator films.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: March 7, 2000
    Assignee: NEC Corporation
    Inventors: Hidemasa Takahashi, Junko Morikawa
  • Patent number: 5834802
    Abstract: A comb-shape MESFET assembly has a plurality of unit FETs including first, second and third groups of unit FETs. The pinch-off voltages of the unit FETs are different from group to group by a step difference. The different pinch-off voltages provide a tailored change in the third-order intermodulation distortion in the output of the MESFET assembly. The step differences in the pinch-off voltage is generated by different thicknesses or impurity concentrations of a semiconductor active layer, different gate length of the unit FETs or different types of stress in the gate insulator films.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: November 10, 1998
    Assignee: NEC Corporation
    Inventors: Hidemasa Takahashi, Junko Morikawa
  • Patent number: 5818077
    Abstract: The field effect transistor includes (a) a plurality of drain finger electrodes, source finger electrodes and gate finger electrodes disposed in an active region on a semiconductor substrate so that each of the gate finger electrodes is sandwiched between each of the drain and source finger electrodes, (b) a source electrode pad for electrically connecting the source finger electrodes to each other, and (c) a gate electrode pad for electrically connecting the gate finger electrodes to each other, the gate electrode pad being disposed farther away from the active region than the source electrode pad. By disposing the gate electrode pad farther away from the active region than the source electrode pad, it is possible to arrange the source electrode pads at higher density, which is accompanied by a lesser number of source finger electrodes associated with each of the source electrode pads. Thus, it is possible to decrease source inductance, and avoid parasitic oscillation.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: October 6, 1998
    Assignee: NEC Corporation
    Inventors: Hidemasa Takahashi, Junko Morikawa, Fumiaki Katano