Abstract: To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a control signal with a host connected to a disk array system; a disk input/output unit that exchanges data and a control signal with a disk; a cache memory that temporarily stores the data during transfer between the host input/output unit and the disk input/output unit in units of segments that are each formed by a plurality of blocks having a predetermined size; an MPU that controls an operation of the control unit by executing a control program; and a cache controller that controls input/output of the data into/from the cache memory, and the host input/output unit transfers, to the cache controller, transfer information containing the guarantee codes of the first blocks of the segments relating to the data transfer.

Abstract: To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a control signal with a host connected to a disk array system; a disk input/output unit that exchanges data and a control signal with a disk; a cache memory that temporarily stores the data during transfer between the host input/output unit and the disk input/output unit in units of segments that are each formed by a plurality of blocks having a predetermined size; an MPU that controls an operation of the control unit by executing a control program; and a cache controller that controls input/output of the data into/from the cache memory, and the host input/output unit transfers, to the cache controller, transfer information containing the guarantee codes of the first blocks of the segments relating to the data transfer.

Abstract: A disk array system having a plurality of disk units includes an upper-level data transfer controller for controlling transfer of data to and from an upper-level apparatus, a data buffer for temporarily storing therein data from the upper-level apparatus, a drive data transfer controller for controlling the data transfer between the buffer and the units, and a main microprocessor for controlling the the transfer controllers. When transferring data, the microprocessor indicates an address to be used in the buffer and a distribution mode of data to the data transfer controllers so that the data transfer is conducted thereafter without intervention of the microprocessor. During the transfer, the microprocessor can generate information for a subsequent data transfer to indicate the information to the transfer controllers. After a data transfer is terminated, the pertinent transfer controller can immediately execute the next data transfer, which increases the utilization efficiency of the data bus.