Patents by Inventor Hidemi Iseki

Hidemi Iseki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4741006
    Abstract: An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a clock signal. The first logic circuit is connected between the output of the D-type flip-flop circuit and the JK terminals of the first flip-flop circuit. The first stage logic circuit includes a first logic circuit section supplied with an up/down mode signal and the output signal of the D-type flip-flop circuit, and a second logic circuit connected in series with with the first logic circuit. Each of the 2nd to the n-th stage logic circuits includes a first logic circuit which is connected between the output terminal of the prestage flip-flop circuit and the JK terminals of the post stage flip-flop circuit, and a second logic circuit section connected to the first logic circuit.
    Type: Grant
    Filed: July 12, 1985
    Date of Patent: April 26, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yamaguchi, Koichi Satoh, Hidemi Iseki, Hiroshi Shigehara
  • Patent number: 4704545
    Abstract: A rectifier circuit is disclosed in which the levels of an input signal and a reference signal are compared, and the polarity of the equivalent resistor is set at positive or negative depending on the result of the comparison. The equivalent resistor is connected, as an input resistor, to a differential amplifier. A feedback resistor is connected between the input and output of the differential amplifier. This arrangement enables the rectifier circuit, with only a single differential amplifier, to perform the rectifying operation with a gain.
    Type: Grant
    Filed: July 3, 1985
    Date of Patent: November 3, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Tanaka, Hidemi Iseki
  • Patent number: 4599580
    Abstract: According to a frequency comparing circuit of the present invention, there is provided a negative switched capacitor circuit having negative equivalent resistance, the value of which is determined according to the reference frequency and the frequency to be compared, and a positive switched capacitor circuit having positive equivalent resistance, the value of which is determined according to the reference frequency. A constant DC voltage is supplied in parallel to one terminal of the two switched capacitor circuits. The respective terminals of the switched capacitor circuits are commonly connected in order to produce the composite current of both output currents of the two switched capacitor circuits. The composite current is integrated by an integrator. Further, there is provided a Schmitt-type oscillating circuit. The oscillating frequency signal from the Schmitt-type oscillating circuit is supplied to the negative switched capacitor circuit.
    Type: Grant
    Filed: November 16, 1984
    Date of Patent: July 8, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yamaguchi, Hiroshi Shigehara, Hidemi Iseki