Abstract: A memory interface control circuit includes an input/output circuit 10 which transmits and receives a data strobe signal DQS to and from a memory, a read control circuit 20 which determines that the data strobe signal DQS associated with a memory read, received from the input/output circuit has repeated a predetermined number of times of transitions based on information on the number of data reads and sets a mask signal MS to a mask state, and a write control circuit 30 which controls a transmission timing of outputting the data strobe signal DQS associated with a memory write from the input/output circuit 10 based on a temporal positional relationship between a data strobe output request signal DQOEN associated with the memory write and the mask signal MS.

Abstract: A memory interface control circuit includes an input/output circuit 10 which transmits and receives a data strobe signal DQS to and from a memory, a read control circuit 20 which determines that the data strobe signal DQS associated with a memory read, received from the input/output circuit has repeated a predetermined number of times of transitions based on information on the number of data reads and sets a mask signal MS to a mask state, and a write control circuit 30 which controls a transmission timing of outputting the data strobe signal DQS associated with a memory write from the input/output circuit 10 based on a temporal positional relationship between a data strobe output request signal DQOEN associated with the memory write and the mask signal MS.

Abstract: A DQS detection circuit 13 detects a preamble of a DQS signal outputted from RAM 11. An up/down counter 14 counts up a number of clock signals CLK) in a period when an DQSEIN signal showing a continuation length of the DQS signal is active, counts down a number of trailing edges of the DQS signal after the preamble corresponding to a data read request, and detects that a counted value is set to 0. A flip-flop circuit FF2 makes a mask signal MS) a low level when the counted value is set to 0. An AND circuit AND2 makes the DQS signal maskable with a mask signal MS.

Abstract: A clock distribution circuit having plural stages of buffers disposed along branch paths for dividing up a clock signal and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, includes in relation to at least one buffer of a plurality of buffers in the same stage on a branch path, a selector for receiving an output of an adjacent buffer located upstream in terms of chain-connection along which the plurality of buffers are connected in testing, and a signal at a branch node corresponding to the at least one buffer by a first input and a second input respectively, selecting one of the first input and the second input based on a select control signal, and supplying the selected input to the one buffer.

Abstract: A DQS detection circuit 13 detects a preamble of a DQS signal outputted from RAM 11. An up/down counter 14 counts up a number of clock signals CLK) in a period when an DQSEIN signal showing a continuation length of the DQS signal is active, counts down a number of trailing edges of the DQS signal after the preamble corresponding to a data read request, and detects that a counted value is set to 0. A flip-flop circuit FF2 makes a mask signal MS) a low level when the counted value is set to 0. An AND circuit AND2 makes the DQS signal maskable with a mask signal MS.

Abstract: A clock distribution circuit having plural stages of buffers disposed along branch paths for dividing up a clock signal and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, includes in relation to at least one buffer of a plurality of buffers in the same stage on a branch path, a selector for receiving an output of an adjacent buffer located upstream in terms of chain-connection along which the plurality of buffers are connected in testing, and a signal at a branch node corresponding to the at least one buffer by a first input and a second input respectively, selecting one of the first input and the second input based on a select control signal, and supplying the selected input to the one buffer.

Abstract: An object of the present invention is to provide a terminating resistor device and a testing method, by which the resistance value of a terminating resistor circuit can be test effectively. The test procedure starts with setting a MUXSCANFF circuit which functions as a selecting circuit in scan mode for test. Then, input a test signal to the scan input and/or clock input. Thereby, a particular resistor element for one bit only is set ON. By detecting the resistance value of this resistor element that has been set ON, it is test whether the one-bit resistance element conforms to manufacturing specification. Select another one of the one-bit resistor elements in order and test each one-bit resistor element, thereby testing all resistor elements.

Abstract: An object of the present invention is to provide a terminating resistor device and a testing method, by which the resistance value of a terminating resistor circuit can be test effectively. The test procedure starts with setting a MUXSCANFF circuit which functions as a selecting circuit in scan mode for test. Then, input a test signal to the scan input and/or clock input. Thereby, a particular resistor element for one bit only is set ON. By detecting the resistance value of this resistor element that has been set ON, it is test whether the one-bit resistance element conforms to manufacturing specification. Select another one of the one-bit resistor elements in order and test each one-bit resistor element, thereby testing all resistor elements.