Patents by Inventor Hidenori Yato

Hidenori Yato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8957884
    Abstract: An integrated circuit device includes: a driving voltage output unit that outputs a driving voltage supplied to a segment electrode of an electro-optical panel; a display data storage unit that stores display data; and a driving waveform information output unit that outputs driving waveform information when a display state of the segment electrode is changed from a first display state corresponding to first display data to a second display state corresponding to second display data, wherein the driving voltage output unit outputs the driving voltage specified by the first display data and the second display data from the display data storage unit, and the driving waveform information from the driving waveform information output unit.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: February 17, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Hidenori Yato, Shigeaki Kawano, Hiroshi Kiya, Keisuke Hashimoto, Hiroaki Nomizo
  • Publication number: 20110069052
    Abstract: An integrated circuit device includes: a driving voltage output unit that outputs a driving voltage supplied to a segment electrode of an electro-optical panel; a display data storage unit that stores display data; and a driving waveform information output unit that outputs driving waveform information when a display state of the segment electrode is changed from a first display state corresponding to first display data to a second display state corresponding to second display data, wherein the driving voltage output unit outputs the driving voltage specified by the first display data and the second display data from the display data storage unit, and the driving waveform information from the driving waveform information output unit.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 24, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hidenori YATO, Shigeaki Kawano, Hiroshi Kiya, Keisuke Hashimoto, Hiroaki Nomizo
  • Patent number: 7067860
    Abstract: The invention can provide a solid-state imaging device that can include a pixel array where a plurality of unit pixels including a photo diode and an insulated gate field effect transistor for detecting photocharges are arranged, and a control circuit that controls the operation of the pixel array. The control circuit can cause a junction region between a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type to be in a forward bias state so as to accumulate a predetermined amount of the charge of a predetermined conductivity type in an accumulation region, and control discharging the charges of a predetermined conductivity type accumulated in the accumulation region thereafter. Accordingly, the invention provides a solid-state imaging element that avoids deterioration of image quality caused by photocharges accumulated during previous imaging.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: June 27, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Hidenori Yato
  • Patent number: 6914228
    Abstract: A solid-state imaging device that can include a pixel array where a plurality of unit pixels including a photo diode and an insulated gate field effect transistor for detecting photocharges are arranged, and a control circuit that controls the operation of the pixel array. The control circuit can include a drain control circuit that provides any of constant voltage, a constant current, and constant charges to a drain diffused region. The control circuit previously forward biases a junction region between a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type by any of the constant voltage, the constant current, and the constant charges, that is provided from the drain control circuit to the drain diffused region, so as to accumulate a predetermined amount of charges of a predetermined conductivity type in an accumulation region, and the charges of a predetermined conductivity type accumulated in the accumulation region are discharged thereafter.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: July 5, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Hidenori Yato
  • Publication number: 20040212031
    Abstract: The invention can provide a solid-state imaging device that can include a pixel array where a plurality of unit pixels including a photo diode and an insulated gate field effect transistor for detecting photocharges are arranged, and a control circuit that controls the operation of the pixel array. The control circuit can cause a junction region between a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type to be in a forward bias state so as to accumulate a predetermined amount of the charge of a predetermined conductivity type in an accumulation region, and control discharging the charges of a predetermined conductivity type accumulated in the accumulation region thereafter. Accordingly, the invention provides a solid-state imaging element that avoids deterioration of image quality caused by photocharges accumulated during previous imaging.
    Type: Application
    Filed: February 11, 2004
    Publication date: October 28, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hidenori Yato
  • Publication number: 20040206991
    Abstract: A solid-state imaging device that can include a pixel array where a plurality of unit pixels including a photo diode and an insulated gate field effect transistor for detecting photocharges are arranged, and a control circuit that controls the operation of the pixel array. The control circuit can include a drain control circuit that provides any of constant voltage, a constant current, and constant charges to a drain diffused region. The control circuit previously forward biases a junction region between a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type by any of the constant voltage, the constant current, and the constant charges, that is provided from the drain control circuit to the drain diffused region, so as to accumulate a predetermined amount of charges of a predetermined conductivity type in an accumulation region, and the charges of a predetermined conductivity type accumulated in the accumulation region are discharged thereafter.
    Type: Application
    Filed: February 6, 2004
    Publication date: October 21, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hidenori Yato
  • Patent number: 5692201
    Abstract: A semiconductor device, microcomputer, or electronic equipment capable of switching internal power voltages in order to suppress the power consumption thereof can prevent erroneous operation of the internal circuitry by switching the level of the internal power voltage in a stepwise manner. A constant-voltage circuit that causes the generation of power voltages is capable of generating voltages of at least three levels. During the switching of the power voltages, a control circuit implements stepwise switching of the power voltages by causing the sequential output of the voltages in increasing or decreasing order of absolute value. Immediately after a switch of power voltage, the level of the signal on the signal line is determined to be at the same level as that before the switching even if a potential change in a signal line is delayed by more than a change in the threshold voltage of a digital circuit, and thus erroneous recognition of data, or rather data inversion, is prevented.
    Type: Grant
    Filed: July 17, 1995
    Date of Patent: November 25, 1997
    Assignee: Seiko Epson Corporation
    Inventor: Hidenori Yato