Patents by Inventor Hideo Harada
Hideo Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240155387Abstract: A user equipment (UE) performs radio communication with a base station that manages a cell including N (N?2) transmission/reception points. The UE comprises: a communicator configured to receive a radio resource control (RRC) message from the base station, the RRC message including information for configuring N beam failure detection resource sets; and a controller configured to individually detect beam failure for each of the N beam failure detection resource sets. The controller is configured to determine, in a case where there is a beam failure detection resource set that does not provide a reference signal resource for detecting the beam failure, the reference signal resource based on a control resource set (CORESET) pool index associated with the beam failure detection resource set.Type: ApplicationFiled: December 26, 2023Publication date: May 9, 2024Inventors: Misa HARADA, Hideaki TAKAHASHI, Takafumi NISHI, Hideo HIMENO
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Publication number: 20240138013Abstract: A user equipment (UE) performs radio communication with a base station that manages a cell including N (N?2) transmission/reception points. The UE comprises: a communicator configured to receive a radio resource control (RRC) message from the base station, the radio resource control (RRC) message including a radio link monitoring configuration for configuring radio link monitoring and a beam failure detection configuration for configuring N beam failure detection resource sets; and a controller configured to detect radio link failure based on the radio link monitoring configuration and individually detect beam failure for each of the N beam failure detection resource sets based on the beam failure detection configuration.Type: ApplicationFiled: December 26, 2023Publication date: April 25, 2024Inventors: Misa Harada, Hideaki Takahashi, Takafumi Nishi, Hideo Himeno
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Publication number: 20240129014Abstract: A user equipment (UE) performs radio communication with a base station that manages a cell including N (N?2) transmission/reception points. The UE comprises: a communicator configured to receive a radio resource control (RRC) message from the base station, the radio resource control (RRC) message including information for configuring N beam failure detection resource sets; and a controller configured to individually detect beam failure for each of the N beam failure detection resource sets. The controller is configured to determine whether or not to initiate a random access procedure for the cell based on a state of recovery from the beam failure in a case where the beam failure has been detected for all of the N beam failure detection resource sets.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Inventors: Misa HARADA, Hideaki TAKAHASHI, Takafumi NISHI, Hideo HIMENO
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Publication number: 20240129015Abstract: A user equipment (UE) performs radio communication with a base station that manages a cell including N (N?2) transmission/reception points. The UE comprises: a communicator configured to receive a radio resource control (RRC) message from the base station, the RRC message including information for configuring N beam failure detection resource sets; and a controller configured to individually detect beam failure for each of the N beam failure detection resource sets. The controller is configured to trigger beam failure recovery (BFR) for one beam failure detection resource set with which the beam failure has been detected. The communicator is configured to cancel all the triggered BFRs for the one beam failure detection resource set in a case where a MAC PDU is transmitted, the MAC PDU including a BFR MAC CE including information regarding the detected beam failure.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Inventors: Misa HARADA, Hideaki Takahashi, Takafumi Nishi, Hideo Himeno
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Publication number: 20240129767Abstract: A user equipment (UE) performs radio communication with a base station that manages a cell including N (N?2) transmission/reception points. The UE comprises: a communicator configured to receive a radio resource control (RRC) message from the base station, the radio resource control (RRC) message including a beam failure detection configuration which is information for configuring N beam failure detection resource sets and is associated with a downlink bandwidth part that is a part of a bandwidth of the cell; and a controller configured to individually detect beam failure for each of the N beam failure detection resource sets in the radio communication using the downlink bandwidth part.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Inventors: Misa HARADA, Hideaki Takahashi, Takafumi Nishi, Hideo Himeno
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Publication number: 20240102924Abstract: A diagnostic optical microscope according to the present embodiment includes at least one laser light source (11) configured to generate laser light for illuminating a sample (40) containing a light absorbing material, a lens configured to focus the laser light to be focused on the sample (40), scanning means for changing a focusing position of the laser light on the sample (40), and a light detector (31) configured to detect laser light transmitted through the sample (40) as signal light. A laser light intensity is changed to obtain a nonlinear region in which the laser light intensity and a signal light intensity have a nonlinear relation due to occurrence of saturation of absorption in the light absorbing material when the laser light intensity is maximized. An image is generated based on a nonlinear component of the signal light based on the saturation of absorption in the light absorbing material.Type: ApplicationFiled: January 19, 2022Publication date: March 28, 2024Inventors: Katsumasa FUJITA, Kentaro NISHIDA, Hikaru SATO, Hideo TANAKA, Yoshinori Harada
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Patent number: 11312929Abstract: Provided are a method of producing a beverage and a method of improving a flavor of a beverage by each of which the imparting of an undesirable aroma is suppressed. The method of producing a beverage according to one embodiment of the present invention is a method of producing a beverage using a raw material liquid, including adding hops that have been subjected to acid treatment to the raw material liquid. The method of improving a flavor of a beverage according to one embodiment of the present invention is a method of improving a flavor of a beverage to be produced using a raw material liquid, including adding hops that have been subjected to acid treatment to the raw material liquid, to thereby improve the flavor of the beverage.Type: GrantFiled: February 6, 2017Date of Patent: April 26, 2022Assignee: Sapporo Breweries LimitedInventors: Susumu Morita, Tomokazu Takaoka, Hideo Harada, Nobuchika Ishibashi, Hajime Kanda, Ryuma Ikutani
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Patent number: 10929273Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.Type: GrantFiled: June 13, 2017Date of Patent: February 23, 2021Assignee: HITACHI, LTD.Inventors: Toru Motoya, Masahiro Shiraishi, Satoshi Nishikawa, Keisuke Yamamoto, Tadanobu Toba, Takumi Uezono, Hideo Harada, Yusuke Kanno
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Patent number: 10747920Abstract: Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.Type: GrantFiled: April 19, 2019Date of Patent: August 18, 2020Assignee: HITACHI, LTD.Inventors: Takumi Uezono, Tadanobu Toba, Masahiro Shiraishi, Hideo Harada, Satoshi Nishikawa
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Publication number: 20190332727Abstract: Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.Type: ApplicationFiled: April 19, 2019Publication date: October 31, 2019Applicant: HITACHI, LTD.Inventors: Takumi UEZONO, Tadanobu TOBA, Masahiro SHIRAISHI, Hideo HARADA, Satoshi NISHIKAWA
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Patent number: 10438383Abstract: The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside.Type: GrantFiled: December 6, 2016Date of Patent: October 8, 2019Assignee: HITACHI, LTD.Inventors: Tadanobu Toba, Takumi Uezono, Yusuke Kanno, Masahiro Shiraishi, Hideo Harada, Satoru Akasaka
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Patent number: 10339242Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.Type: GrantFiled: June 14, 2017Date of Patent: July 2, 2019Assignee: Hitachi, Ltd.Inventors: Takumi Uezono, Tadanobu Toba, Yusuke Kanno, Masahiro Shiraishi, Hideo Harada, Satoshi Nishikawa, Toru Motoya
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Patent number: 10313095Abstract: A control system includes an arithmetic device configured of an A system arithmetic unit including a data dividing unit, a B system arithmetic unit including a data dividing unit, and an A system communication control unit including a data combining unit and a collation unit, wherein the A system arithmetic unit and the B system arithmetic unit have a duplex configuration, the A system arithmetic unit and the B system arithmetic unit are separated by a gap, a frame output from the A system arithmetic unit is transmitted to a B system communication control unit through the A system communication control unit and an interface element, and a frame output from the B system arithmetic unit is transmitted to the A system communication control unit through the B system communication control unit and an interface element.Type: GrantFiled: October 10, 2017Date of Patent: June 4, 2019Assignee: Hitachi, Ltd.Inventors: Katsunobu Natori, Tetsuya Nakajima, Satoshi Nishikawa, Masahiro Shiraishi, Hideo Harada
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Publication number: 20190119613Abstract: Provided are a method of producing a beverage and a method of improving a flavor of a beverage by each of which the imparting of an undesirable aroma is suppressed. The method of producing a beverage according to one embodiment of the present invention is a method of producing a beverage using a raw material liquid, including adding hops that have been subjected to acid treatment to the raw material liquid. The method of improving a flavor of a beverage according to one embodiment of the present invention is a method of improving a flavor of a beverage to be produced using a raw material liquid, including adding hops that have been subjected to acid treatment to the raw material liquid, to thereby improve the flavor of the beverage.Type: ApplicationFiled: February 6, 2017Publication date: April 25, 2019Applicant: Sapporo Holdings LimitedInventors: Susumu Morita, Tomokazu Takaoka, Hideo Harada, Nobuchika Ishibashi, Hajime Kanda, Ryuma Ikutani
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Publication number: 20180115405Abstract: A control system includes an arithmetic device configured of an A system arithmetic unit including a data dividing unit, a B system arithmetic unit including a data dividing unit, and an A system communication control unit including a data combining unit and a collation unit, wherein the A system arithmetic unit and the B system arithmetic unit have a duplex configuration, the A system arithmetic unit and the B system arithmetic unit are separated by a gap, a frame output from the A system arithmetic unit is transmitted to a B system communication control unit through the A system communication control unit and an interface element, and a frame output from the B system arithmetic unit is transmitted to the A system communication control unit through the B system communication control unit and an interface element.Type: ApplicationFiled: October 10, 2017Publication date: April 26, 2018Inventors: Katsunobu NATORI, Tetsuya NAKAJIMA, Satoshi NISHIKAWA, Masahiro SHIRAISHI, Hideo HARADA
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Publication number: 20170364610Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.Type: ApplicationFiled: June 14, 2017Publication date: December 21, 2017Inventors: Takumi UEZONO, Tadanobu TOBA, Yusuke KANNO, Masahiro SHIRAISHI, Hideo HARADA, Satoshi NISHIKAWA, Toru MOTOYA
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Publication number: 20170357567Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.Type: ApplicationFiled: June 13, 2017Publication date: December 14, 2017Applicant: HITACHI, LTD.Inventors: Toru MOTOYA, Masahiro SHIRAISHI, Satoshi NISHIKAWA, Keisuke YAMAMOTO, Tadanobu TOBA, Takumi UEZONO, Hideo HARADA, Yusuke KANNO
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Publication number: 20170249760Abstract: The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside.Type: ApplicationFiled: December 6, 2016Publication date: August 31, 2017Inventors: Tadanobu TOBA, Takumi UEZONO, Yusuke KANNO, Masahiro SHIRAISHI, Hideo HARADA, Satoru AKASAKA
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Patent number: 9023476Abstract: Disclosed is a resin particle having excellent low-temperature fusibility, having a sufficiently narrow size distribution, and that is obtained using a liquid or supercritical fluid. In the resin particle (C), which comprises a microparticle (A) containing a resin (a) being coated to or adhered to the surface of a resin particle (B) that contains another resin (b), the degree of swelling of the microparticle (A) resulting from liquid or supercritical carbon dioxide (X) at a temperature less than the glass transition temperature or the melting point of the microparticle (A) is no greater than 16%, and with the resin (a) as a constituent unit, the resin particle (C) contains 0.1-50 wt % of a non-crystalline non-halogen vinyl monomer (m1) of which the solubility parameter (SP value: (cal/cm3)1/2) is 7-9.Type: GrantFiled: May 27, 2011Date of Patent: May 5, 2015Assignee: Sanyo Chemical Industries, Ltd.Inventors: Hideo Harada, Kenta Nose, Masaru Honda, Eiji Iwawaki, Takahiro Tanaka
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Publication number: 20130071665Abstract: Disclosed is a resin particle having excellent low-temperature fusibility, having a sufficiently narrow size distribution, and that is obtained using a liquid or supercritical fluid. In the resin particle (C), which comprises a microparticle (A) containing a resin (a) being coated to or adhered to the surface of a resin particle (B) that contains another resin (b), the degree of swelling of the microparticle (A) resulting from liquid or supercritical carbon dioxide (X) at a temperature less than the glass transition temperature or the melting point of the microparticle (A) is no greater than 16%, and with the resin (a) as a constituent unit, the resin particle (C) contains 0.1-50 wt % of a non-crystalline non-halogen vinyl monomer (m1) of which the solubility parameter (SP value: (cal/cm3)1/2) is 7-9.Type: ApplicationFiled: May 27, 2011Publication date: March 21, 2013Applicant: SANYO CHEMICAL INDUSTRIES, LTD.Inventors: Hideo Harada, Kenta Nose, Masaru Honda, Eiji Iwawaki, Takahiro Tanaka