Patents by Inventor Hideo Nakano

Hideo Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155736
    Abstract: A first data center includes a first virtual network that provides a communication service in cooperation with at least a part of a communication facility of a first communication operator and a first communication unit that is operable to communicate with a second data center. The second data center includes a second virtual network that provides a communication service in cooperation with at least a part of a communication facility of a second communication operator and a second communication unit that is operable to communicate with the first data center. The first communication unit is operable to transmit to the second communication unit, communication data to be transmitted from a first terminal connecting to the first virtual network via a communication facility of the first communication operator to a second terminal connecting via a communication facility of the second communication operator to the second virtual network.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: NEC CORPORATION
    Inventors: Shintaro NAKANO, Hideo HASEGAWA, Satoru ISHII
  • Publication number: 20240107601
    Abstract: A datacenter, a communication apparatus, a communication method, and a communication control method in a communication system are provided that can enhance the versatility of a datacenter and a virtual network constructed therein. A communication system includes: a plurality of wireless communication facilities owned by a plurality of network operators, respectively; and a datacenter in which a virtual core network is constructed, wherein the virtual core network implements mobile communication functions by using the plurality of wireless communication facilities.
    Type: Application
    Filed: December 12, 2023
    Publication date: March 28, 2024
    Applicant: NEC Corporation
    Inventors: Shintaro NAKANO, Hideo Hasegawa, Satoru Ishii
  • Patent number: 11374752
    Abstract: Disclosed are devices, systems and methods for performing secure transactions in an aircraft are disclosed. Embodiments of the disclosed technology enable low cost carriers to provide payment verification for on-board purchases via the in-flight entertainment system. An exemplary method for performing secure transactions in an aircraft includes transmitting, by a user device in the aircraft using a wireless protocol, a first authentication factor and a request for one or more on-board services; receiving, from an on-board transceiver using the wireless protocol, an authentication token (a) comprising a one-time code and (b) encrypted using an asymmetric cryptographic algorithm; transmitting, using the asymmetric cryptographic algorithm, a second authentication factor comprising (a) the authentication token and (b) a text message transmitted from the user device; and receiving a confirmation of a delivery of the one or more on-board services.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: June 28, 2022
    Assignee: PANASONIC AVIONICS CORPORATION
    Inventor: Hideo Nakano
  • Patent number: 10975376
    Abstract: The present invention is intended to provide a highly versatile and simple technique which can increase the expression level of a protein in an E. coli expression system or a yeast expression system. Using an E. coli expression system or a yeast expression system, a target protein is expressed as a tag-added protein to which a peptide tag composed of an amino acid sequence SK, SKX, SKXX (SEQ ID NO. 1), AKXX (SEQ ID NO. 29), or KKXX (SEQ ID NO. 30) (wherein X represents any amino acid residue) is linked at the N-terminal.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 13, 2021
    Assignee: National University Corporation Nagoya University
    Inventors: Hideo Nakano, Teruyo Kato
  • Publication number: 20200389307
    Abstract: Disclosed are devices, systems and methods for performing secure transactions in an aircraft are disclosed. Embodiments of the disclosed technology enable low cost carriers to provide payment verification for on-board purchases via the in-flight entertainment system. An exemplary method for performing secure transactions in an aircraft includes transmitting, by a user device in the aircraft using a wireless protocol, a first authentication factor and a request for one or more on-board services; receiving, from an on-board transceiver using the wireless protocol, an authentication token (a) comprising a one-time code and (b) encrypted using an asymmetric cryptographic algorithm; transmitting, using the asymmetric cryptographic algorithm, a second authentication factor comprising (a) the authentication token and (b) a text message transmitted from the user device; and receiving a confirmation of a delivery of the one or more on-board services.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventor: Hideo Nakano
  • Publication number: 20200032275
    Abstract: The present invention is intended to provide a highly versatile and simple technique which can increase the expression level of a protein in an E. coli expression system or a yeast expression system. Using an E. coli expression system or a yeast expression system, a target protein is expressed as a tag-added protein to which a peptide tag composed of an amino acid sequence SK, SKX, SKXX, AKXX, or KKXX (wherein X represents any amino acid residue) is linked at the N-terminal.
    Type: Application
    Filed: June 15, 2016
    Publication date: January 30, 2020
    Applicant: National University Corporation Nagoya University
    Inventors: Hideo Nakano, Teruyo Kato
  • Patent number: 10089910
    Abstract: In the image display device, the vignetting pattern generator generates a vignetting pattern image composed of image data having inverted brightness characteristics obtained by inverting brightness characteristics of a panel of the liquid crystal display. The display controller carries out control to cause a pattern image obtained by combining a flat pattern image in gray composed of image data having a uniform grayscale level and the vignetting pattern image to be displayed on the liquid crystal display. And the correction data calculator calculates correction data for correcting brightness unevenness of an input image based on brightness values of image data of captured images obtained by imaging, by the camera, the pattern images displayed on the liquid crystal display.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 2, 2018
    Assignee: MegaChips Corporation
    Inventors: Hitoshi Sugiyama, Hideo Nakano, Junichi Komine
  • Publication number: 20160163252
    Abstract: In the image display device, the vignetting pattern generator generates a vignetting pattern image composed of image data having inverted brightness characteristics obtained by inverting brightness characteristics of a panel of the liquid crystal display. The display controller carries out control to cause a pattern image obtained by combining a flat pattern image in gray composed of image data having a uniform grayscale level and the vignetting pattern image to be displayed on the liquid crystal display. And the correction data calculator calculates correction data for correcting brightness unevenness of an input image based on brightness values of image data of captured images obtained by imaging, by the camera, the pattern images displayed on the liquid crystal display.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 9, 2016
    Applicant: MegaChips Corporation
    Inventors: Hitoshi Sugiyama, Hideo Nakano, Junichi Komine
  • Patent number: 7790468
    Abstract: A test object receptacle, capable of measuring a test object in a wide range of concentrations with good accuracy and within a short time, contains a plurality of fine protruding portions inside grooves. The test object receptacle can fix antigens, antibodies and test objects faster than without the protruding portions. Furthermore, the protruding portions are so formed that the surface area thereof increases gradually to the downstream with respect to the movement direction of the test object in the grooves, the detection intensity (intensity of color development) of the test object is not saturated downstream of the grooves even when the test object has a high concentration. For this reason, the test object can be detected within a short time and the measurements can be conducted within a wide concentration range.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: September 7, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Chisato Yoshimura, Hideo Nakano, Takanori Ishishika
  • Patent number: 7642848
    Abstract: A variable gain amplifying apparatus has an amplifier, one or more first switching elements connected in parallel to the amplifier, and a phase shifter connected in series to the first switching element. The first switching element is enabled if the level of an input signal or an output signal is higher than a predetermined level, and the first switching element is disabled if the level of the input signal or the output signal is equal to or lower than the predetermined level. The amplifier does not operate when the first switching element is enabled, and the amplifier operates when the first switching element is disabled, and the amount of phase shift when the input signal is passed through the amplifier and phase shifter is substantially equal to the amount of phase shift when the input signal is passed through the first switching element.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: January 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Toshifumi Nakatani, Jyunji Itoh, Hideo Nakano
  • Publication number: 20080265994
    Abstract: A variable gain amplifying apparatus has an amplifier, one or more first switching elements connected in parallel to the amplifier, and a phase shifter connected in series to the first switching element. The first switching element is enabled if the level of an input signal or an output signal is higher than a predetermined level, and the first switching element is disabled if the level of the input signal or the output signal is equal to or lower than the predetermined level. The amplifier does not operate when the first switching element is enabled, and the amplifier operates when the first switching element is disabled, and the amount of phase shift when the input signal is passed through the amplifier and phase shifter is substantially equal to the amount of phase shift when the input signal is passed through the first switching element.
    Type: Application
    Filed: January 9, 2008
    Publication date: October 30, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toshifumi Nakatani, Jyunji Itoh, Hideo Nakano
  • Patent number: 7342442
    Abstract: A variable gain amplifying apparatus has an amplifier, one or more first switching elements connected in parallel to the amplifier, and a phase shifter connected in series to the first switching element. The first switching element is enabled if the level of an input signal or an output signal is higher than a predetermined level, and the first switching element is disabled if the level of the input signal or the output signal is equal to or lower than the predetermined level. The amplifier does not operate when the first switching element is enabled, and the amplifier operates when the first switching element is disabled, and the amount of phase shift when the input signal is passed through the amplifier and phase shifter is substantially equal to the amount of phase shift when the input signal is passed through the first switching element.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: March 11, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshifumi Nakatani, Jyunji Itoh, Hideo Nakano
  • Patent number: 7298205
    Abstract: An amplifier circuit amplifies a signal inputted from an input terminal. A first feedback circuit is placed across an emitter of a bipolar transistor and an input of the amplifier circuit. A second feedback circuit is placed across the input and an output of the amplifier circuit for feeding the output of the amplifier circuit back to the input of the amplifier circuit. A phase change amount in the feedback circuit is determined by the values of an inductor and a capacitor. The values of these elements are selected so that a phase of a signal in which fundamental waves included in two feedback signals are combined and a phase of a signal in which second harmonics included in the two feedback signals are combined are shifted by approximately 180 degrees from a phase of a fundamental wave of an input signal.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: November 20, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshifumi Nakatani, Jyunji Itoh, Hideo Nakano
  • Patent number: 7123073
    Abstract: An amplifier circuit amplifies a differential signal supplied by a pair of input terminals. A phase controller circuit is placed between the emitters of two bipolar transistors and the ground. A feedback circuit is placed across the input and the output of the amplifier circuit for feeding the output of the amplifier circuit back to the input thereof. A phase change amount in the amplifier circuit is determined by the values of two inductors, whereas a phase change amount in the feedback circuit is determined by the values of two resistances and capacitors. The values of these devices are selected so that a phase difference between an input signal and a feedback signal is approximately 180 degrees in a range from the frequency of a fundamental wave of the input signal to the frequency of a second harmonic thereof.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: October 17, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshifumi Nakatani, Jyunji Itoh, Hideo Nakano
  • Publication number: 20060176112
    Abstract: A variable gain amplifying apparatus has an amplifier, one or more first switching elements connected in parallel to the amplifier, and a phase shifter connected in series to the first switching element. The first switching element is enabled if the level of an input signal or an output signal is higher than a predetermined level, and the first switching element is disabled if the level of the input signal or the output signal is equal to or lower than the predetermined level. The amplifier does not operate when the first switching element is enabled, and the amplifier operates when the first switching element is disabled, and the amount of phase shift when the input signal is passed through the amplifier and phase shifter is substantially equal to the amount of phase shift when the input signal is passed through the first switching element.
    Type: Application
    Filed: March 28, 2006
    Publication date: August 10, 2006
    Inventors: Toshifumi Nakatani, Jyunji Itoh, Hideo Nakano
  • Publication number: 20050202733
    Abstract: A test object receptacle, capable of measuring a test object in a wide range of concentrations with good accuracy and within a short time, contains a plurality of fine protruding portions inside grooves. The test object receptacle can fix antigens, antibodies and test objects faster than without the protruding portions. Furthermore, the protruding portions are so formed that the surface area thereof increases gradually to the downstream with respect to the movement direction of the test object in the grooves, the detection intensity (intensity of color development) of the test object is not saturated downstream of the grooves even when the test object has a high concentration. For this reason, the test object can be detected within a short time and the measurements can be conducted within a wide concentration range.
    Type: Application
    Filed: March 4, 2005
    Publication date: September 15, 2005
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Chisato Yoshimura, Hideo Nakano, Takanori Ishishika
  • Publication number: 20050156277
    Abstract: There is provided a semiconductor device, wherein a digital circuit region and an analog circuit region are located independently. A power supply wiring and a ground wiring are placed on the periphery of each circuit region and are connected to elements in each circuit region. A MOS capacitor is formed under the power supply wiring and the ground wiring. The terminals of the MOS capacity are connected to the power supply wiring and the ground wiring. Pads are placed in each circuit region surrounded by the power supply wiring, the ground wiring, and the MOS capacitor and are connected to the elements of each circuit region.
    Type: Application
    Filed: December 15, 2004
    Publication date: July 21, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hideo Nakano, Shoji Yoshida, Masakatsu Maeda
  • Publication number: 20050110555
    Abstract: An amplifier circuit (15) amplifies a differential signal supplied by a pair of input terminals ( {P1+, P1?}). A phase controller circuit (25) is placed between the emitters of bipolar transistors (101a, 101b) and the ground. A feedback circuit (35) is placed across the input and the output of the amplifier circuit (15) for feeding the output of the amplifier circuit (15) back to the input thereof. A phase change amount in the amplifier circuit (15) is determined by the values of inductors (201a, 201b), whereas a phase change amount in the feedback circuit (35) is determined by the values of resistances (301a, 301b) and capacitors (302a, 302b). The values of these devices are selected so that a phase difference between an input signal and a feedback signal is approximately 180 degrees in a range from the frequency of a fundamental wave of the input signal to the frequency of a second harmonic thereof.
    Type: Application
    Filed: March 18, 2003
    Publication date: May 26, 2005
    Inventors: Toshifumi Nakatani, Jyunji Itoh, Hideo Nakano
  • Publication number: 20050062540
    Abstract: An amplifier circuit 10 amplifies a signal inputted from an input terminal P1. A first feedback circuit 20 is placed across an emitter of a bipolar transistor 101 and an input of the amplifier circuit 10. A second feedback circuit 30 is placed across the input and an output of the amplifier circuit 10 for feeding the output of the amplifier circuit 10 back to the input. A phase change amount in the feedback circuit is determined by the values of an inductor and a capacitor. The values of these elements are selected so that a phase of a signal in which fundamental waves included in two feedback signals are combined and a phase of a signal in which second harmonics included in the two feedback signals are combined are shifted by approximately 180 degrees from a phase of a fundamental wave of an input signal.
    Type: Application
    Filed: September 22, 2004
    Publication date: March 24, 2005
    Inventors: Toshifumi Nakatani, Jyunji Itoh, Hideo Nakano
  • Patent number: 6704027
    Abstract: The present invention was made to solve the problem that users cannot check e-mail containing an attached image at a glance on conventional portable terminals. According to the present invention, there is provided a portable terminal that can display the e-mail text overlapped upon the attached image in an easy-to-see manner, and hence improve its usability as a mail receiving terminal. An image processing/output means converts the attached image data into image data of a size corresponding to that of the display area, and processes the attached image data to correct either of the brightness and contrast thereof. Further, a character setting/output means sets display color of the mail text according to the chromaticity of the image data so that the mail text will be overlapped upon and displayed with the set display color against the background of the processed image.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: March 9, 2004
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Hideo Nakano