Abstract: A microcontroller is disposed on a receiving part of a wireless system in order to process a demodulation signal generated by a receiver circuit, and includes a memory and a CPU. The memory stores a control program of the microcontroller. The control program thereof includes a dual loop routine for an operation in reception standby mode. The dual loop routine has a first loop and a second loop included in the first loop. The CPU has an instruction set consisting of a plurality of instructions, and executes the instructions according to the program stored in the memory. The CPU executes an instruction irrelevant to an operation when the microcontroller is in reception mode during the second loop a number of times. The number of times is at least such that noise caused by the repetition of the second loop is lowered below a desired level.

Abstract: An input circuit for receiving an input signal supplied to an input terminal includes a capacitor having one end connected to the input terminal and a capacitor driving circuit for converting the input signal into a signal having positive logic that is the same as logic of the input signal and supplying the converted signal to the other end of the capacitor so as to drive the capacitor.

Abstract: An input circuit for receiving an input signal supplied to an input terminal includes a capacitor having one end connected to the input terminal and a capacitor driving circuit for converting the input signal into a signal having positive logic that is the same as logic of the input signal and supplying the converted signal to the other end of the capacitor so as to drive the capacitor.

Abstract: Even when, for example, electric charge is injected into the output transistor due to external factor such as a noise from the outside, to prevent the step-down voltage from rising, the step-down circuit is comprised of an N channel type output transistor which controls the voltage at the control end, a booster, which is connected to the control end of the output transistor and raises the voltage at the control end and a discharge circuit, which discharges the electric charge at the control end of the output transistor so that the power supply voltage inputted from the input end is stepped down to a desired step-down voltage and outputted from the output end.

Abstract: An oscillator circuit includes a capacitance element; an inverter outputting an inverted voltage at a first terminal of the capacitance element; a voltage source including a resistor and an NMOS transistor connected in series between a first high-potential power supply and a ground power supply and outputting a voltage from a node to which the resistor and the NMOS transistor are connected; a switch circuit connecting a second terminal of the capacitance element to the voltage source or the ground power supply in accordance with the voltage output from the inverter; and a constant-current source connected to a second high-potential power supply and allowing, regardless of changes in the voltage and temperature of the second high-potential power supply within certain ranges, flow of a constant current into or out of the first terminal of the capacitance element in accordance with the voltage output from the inverter.

Abstract: An object is not only to contribute to reduction in current consumption but also to advance actuation of a system required in a camera, an on-vehicle electric component, etc. by shortening a waiting time for stabilization of oscillation. An oscillator having an inverting amplifier inverting and amplifying an input signal and outputting it, a resonator connected to between an input and an output terminals of the inverting amplifier, a feedback resistance connected in parallel to the resonator, and an output circuit outputting a first clock signal based on a signal of an on-load parallel resonance frequency or a parallel resonance frequency oscillated by the resonator, the inverting amplifier and the feedback resistance to a function block is provided.

Abstract: An input circuit (a first transistor pair) that receives complementary input signals is connected to a latch circuit (a second transistor pair) that converts the amplitude of an input signal into second amplitude higher than first amplitude. A current mirror circuit (a third transistor pair) is disposed between the latch circuit and a high-level power supply line. The current mirror circuit makes a source voltage of the second transistors being turned on lower than the source voltage of the second transistors being turned off. The second transistors being turned on are likely to be turned off although the on-current of corresponding first transistors is low. To the contrary, the second transistors being turned off are likely to be turned on. Accordingly, even when a voltage of a high logic level of an input signal is low, the level conversion circuit can surely operate without malfunction.

Abstract: A semiconductor device in which a dielectric breakdown of a gate oxide in a MOS capacitor can be prevented and in which a circuit area can be reduced. The semiconductor device comprises an NMOS transistor a gate of which is connected to a terminal VDD on a high potential side and a PMOS transistor a gate of which is connected to a terminal GND on a low potential side, source/drain (S/D) regions of the NMOS transistor and source/drain (S/D) regions of the PMOS transistor being electrically connected.

Abstract: A microcontroller is disposed on a receiving part of a wireless system in order to process a demodulation signal generated by a receiver circuit, and includes a memory and a CPU. The memory stores a control program of the microcontroller. The control program thereof includes a dual loop routine for an operation in reception standby mode. The dual loop routine has a first loop and a second loop included in the first loop. The CPU has an instruction set consisting of a plurality of instructions, and executes the instructions according to the program stored in the memory. The CPU executes an instruction irrelevant to an operation when the microcontroller is in reception mode during the second loop a number of times. The number of times is at least such that noise caused by the repetition of the second loop is lowered below a desired level.

Abstract: An input circuit (a first transistor pair) that receives complementary input signals is connected to a latch circuit (a second transistor pair) that converts the amplitude of an input signal into second amplitude higher than first amplitude. A current mirror circuit (a third transistor pair) is disposed between the latch circuit and a high-level power supply line. The current mirror circuit makes a source voltage of the second transistors being turned on lower than the source voltage of the second transistors being turned off. The second transistors being turned on are likely to be turned off although the on-current of corresponding first transistors is low. To the contrary, the second transistors being turned off are likely to be turned on. Accordingly, even when a voltage of a high logic level of an input signal is low, the level conversion circuit can surely operate without malfunction.

Abstract: An object is not only to contribute to reduction in current consumption but also to advance actuation of a system required in a camera, an on-vehicle electric component, etc. by shortening a waiting time for stabilization of oscillation. An oscillator having an inverting amplifier inverting and amplifying an input signal and outputting it, a resonator connected to between an input and an output terminals of the inverting amplifier, a feedback resistance connected in parallel to the resonator, and an output circuit outputting a first clock signal based on a signal of an on-load parallel resonance frequency or a parallel resonance frequency oscillated by the resonator, the inverting amplifier and the feedback resistance to a function block is provided.

Abstract: Even when, for example, electric charge is injected into the output transistor due to external factor such as a noise from the outside, to prevent the step-down voltage from rising, the step-down circuit is comprised of an N channel type output transistor which controls the voltage at the control end, a booster, which is connected to the control end of the output transistor and raises the voltage at the control end and a discharge circuit, which discharges the electric charge at the control end of the output transistor so that the power supply voltage inputted from the input end is stepped down to a desired step-down voltage and outputted from the output end.

Abstract: A semiconductor device in which a dielectric breakdown of a gate oxide in a MOS capacitor can be prevented and in which a circuit area can be reduced. The semiconductor device comprises an NMOS transistor a gate of which is connected to a terminal VDD on a high potential side and a PMOS transistor a gate of which is connected to a terminal GND on a low potential side, source/drain (S/D) regions of the NMOS transistor and source/drain (S/D) regions of the PMOS transistor being electrically connected.

Abstract: An AD converter includes a sample-&-hold circuit which samples and holds an input analog potential in a first period, and generates a signal indicative of a magnitude relation between the held input analog potential and a reference potential in a second period, a plurality of amplifiers connected in series which amplify an output of the sample-&-hold circuit, and a control circuit which controls operating timing of the amplifiers so as to make at least one of the amplifiers start operating in a middle of the first period.

Abstract: An AD converter includes a sample-&-hold circuit which samples and holds an input analog potential in a first period, and generates a signal indicative of a magnitude relation between the held input analog potential and a reference potential in a second period, a plurality of amplifiers connected in series which amplify an output of the sample-&-hold circuit, and a control circuit which controls operating timing of the amplifiers so as to make at least one of the amplifiers start operating in a middle of the first period.

Abstract: An analog switch circuit with superior breakdown voltage characteristics that can operate at a high speed at a low power supply voltage. The analog switch circuit includes a comparator circuit for inputting and comparing an analog input signal input to an analog switch section and a reference signal. If the input potential of the analog input signal is lower than the reference potential of the reference signal, a voltage boost circuit sets a potential of a gate of an n MOS transistor included in the analog switch section to a potential of positive power supply voltage. If the input potential of the analog input signal is higher than the reference potential of the reference signal, the voltage boost circuit boosts the potential of the gate to a potential higher than the potential of power supply voltage.

Abstract: A semiconductor chip has a circuit block, a power supply line and a ground line. A condenser chip in which a noise reduction condenser connected to the circuit block is stacked on the semiconductor chip. Because the condenser chip is stacked on the semiconductor chip, it is not necessary to provide a noise reduction condenser on the semiconductor chip and also not to provide a noise reduction condenser on a substrate on which the semiconductor chip is mounted.

Abstract: An analog switch circuit with superior breakdown voltage characteristics that can operate at a high speed at a low power supply voltage. The analog switch circuit includes a comparator circuit for inputting and comparing an analog input signal input to an analog switch section and a reference signal. If the input potential of the analog input signal is lower than the reference potential of the reference signal, a voltage boost circuit sets a potential of a gate of an n MOS transistor included in the analog switch section to a potential of positive power supply voltage. If the input potential of the analog input signal is higher than the reference potential of the reference signal, the voltage boost circuit boosts the potential of the gate to a potential higher than the potential of power supply voltage.

Abstract: An A/D converter includes a capacitor type D/A conversion circuit including a capacitor array constituted of a plurality of capacitors for sampling an input potential and storing electric charge, a first resistor type D/A conversion circuit for generating a desired potential by potential division, a second resistor type D/A conversion circuit for generating a desired potential by potential division, a first signal path for adding an output of the first resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling; a second signal path for adding an output of the second resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling, and a comparing circuit for determining whether an output potential of the capacitor type D/A conversion circuit is higher or lower than an input potential, and thereby the circuit with processing time of A/D conversion being shortened can be provided.

Abstract: An A/D converter includes a capacitor type D/A conversion circuit including a capacitor array constituted of a plurality of capacitors for sampling an input potential and storing electric charge, a first resistor type D/A conversion circuit for generating a desired potential by potential division, a second resistor type D/A conversion circuit for generating a desired potential by potential division, a first signal path for adding an output of the first resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling; a second signal path for adding an output of the second resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling, and a comparing circuit for determining whether an output potential of the capacitor type D/A conversion circuit is higher or lower than an input potential, and thereby the circuit with processing time of A/D conversion being shortened can be provided.