Abstract: A memory circuit incorporating a current-mirror type amplifier which directly amplifies a varied potential of a pair of bit lines. As soon as the word line goes High, the current-mirror type amplifier is simultaneously activated to amplify a minimal difference (100 mV) of potential between these bit lines. Data signal outputted from the current-mirror type amplifier is then transmitted to a read-only signal line. As a result, data is quickly read out before a built-in sense amplifier completes amplification, thus quickly achieving an accessing operation at extremely fast speed.

Abstract: A dynamic random access memory (DRAM) having a plurality of word lines and a plurality of bit line pairs comprises circuitry for applying an equalizing potential to either one or the other bit line of the paired bit lines to equalize (1) a first difference between a first potential and a second potential and (2) a second difference between the first potential and a third potential, for balanced read out of the paired bit lines. The first potential appears on a reference bit line paired with a bit line connected to a memory cell selected by an external address prior to sensing thereof, the second potential appears on the bit line when the selected memory cell contains "H" level data and the third potential appears on the bit line when the selected memory cell contains "L" level data.

Abstract: Transfer transistors are connected midway on respective bit lines of a bit line pair. Memory cells are provided for a first bit line pair and a second bit line pair partitioned by the transfer transistor, and a sense amplifier is connected to the first bit line pair. When a memory cell connected to the first bit line pair is selected, the transfer transistor turns off. Therefore, the potential difference appears only on the first bit line pair, with the potentials amplified by the sense amplifier. In this state, the potential of the second bit line pair is not changed and not amplified.

Abstract: A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal We having a shorter duration than that of the signal W at down edge of the signal W as a trigger. The output signal We of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

Abstract: An input protective apparatus for a semiconductor device (Q3) comprises an MOS transistor (Q4) having a thick gate insulating film formed therein. The MOS transistor (Q4) has one active layer connected to an input terminal (11) through a second resistor element (R2) and connected to a semiconductor device (Q3) to be protected through a first resistor element (R1), and an other active layer connected to a ground terminal. The input protective apparatus is adapted such that a resistance value R.sub.1 of a first resistor element (R1) and a resistance value R.sub.2 of the second resistor element (R2) satisfy the relation R.sub.1 >R.sub.2, and the on-resistance R.sub.3 of the MOS transistor (Q4) and the resistance value R.sub.2 satisfy the relation R.sub.3 <<R.sub.2.

Abstract: P-type sense amplifier and N-type sense amplifier are connected to each of bit lines in a pair of bit lines respectively. N-channel MOS transistor is connected to each of the bit lines between the P-type sense amplifier and the N-type sense amplifier, and normally turned on. Each of a plurality of memory cells is connected to any of the bit lines at the side of the N-type sense amplifier from the transistor. The power source potential generated by the P-type sense amplifier is dropped by the threshold voltage of the transistor and supplied to one of the bit liens to which the memory cells are connected. The ground potential generated by the N-type sense amplifier is supplied without changing the potential to other of the bit lines.

Abstract: A DRAM comprises equalizing capacitance for equalizing the difference between a potential on a bit line to which a selected memory cell is connected and a potential on a reference bit line paired with the bit line when the selected memory cell stores "H" information and that when the selected memory cell stores "L" information, before sensing operation is started. The amplitude of a potential on a selected word line is at an operating power-supply voltage Vcc level of the DRAM.

Abstract: A semiconductor dynamic random access memory is provided comprising bit line pairs divided into groups and sense amplifiers, one for each bit line pair group provided on one side of the bit line pairs in a line. When a word line is selected, only one bit line pair is released from a precharge.equalize state to be connected to a corresponding sense amplifier in each bit line pair group in accordance with address information of the word line. Memory cells are arranged such that only one memory cell is connected to the selected word line in each bit line pair group.

Abstract: A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal W having a shorter duration than that of the signal W at a down edge of the signal W as a trigger. The output signal W of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

Abstract: A word line driving signal generating circuit and a sense amplifier activating signal generating circuit are provided for every partitioned memory cell array. When the levels of an external RAS signal and an external CAS signal have a predetermined relation and an external RNC signal remains at a predetermined potential or more, a refresh operation is started. A refresh address is generated from a refresh address counter in a sense restore control circuit. All of the memory cell arrays are simultaneously refreshed in response to the address. On this occasion, an operation for selecting a column by a column decoder provided in each of the memory cell arrays is inhibited. In the case in which an input of the external RNC signal is not prepared, when the levels of the external RAS signal and the external CAS signal have a predetermined relation and this state is held in a predetermined time period or more, the same refresh operation as described above is started.

Abstract: In a DRAM device in accordance with the present invention, when a memory cell is selected for reading or writing data, at least one of the bit lines adjacent to the bit lines related with the selected memory cell is not selected simultaneously. Consequently, loss in a sense margin due to capacitance coupling between adjacent bit lines can be reduced.

Abstract: A semiconductor memory comprises a data bit memory cell array (3), a check bit memory cell array (4), and an address decoder (19) which includes a switching circuit (20) for selectively accessing data from either the memory cell array (3) or (4). Decoding signals d.sub.l to d.sub.m are used for reading out data latched by a column address strobe (CAS) signal. The decoding signals are applied to either the memory cell array (3) or (4) through a group of switching elements selectively rendered conductive by complementary signals .phi. and .phi.. The logical values of the signals .phi. and .phi. change responsive to a change in the CAS signal state.

Abstract: A semiconductor memory device such as a static RAM (Random Access Memory) device comprises a ground connection circuit of n channel field effect transistors connected between two I/O lines and the ground. The precharge circuit for precharging and the ground connection circuit both operate in response to the signal which is in synchronization with an externally applied external chip select signal. Therefore, the access delay derived from the fluctuation of the supply voltage generated before the change of the external chip select signal can be prevented.

Abstract: A memory device provides a test mode which simultaneously carries out the function test of plural bit memory cells. In this memory device, trilevel decision is carried out based on the AND operation on the memory cell information of the selected plural bits in the single device level while bilevel decision is carried out in the board level on the basis of the OR operation on the AND result of the information of the selected plural bit memory cells and the AND result of the inverted information of the same.

Abstract: A circuit for generating a boosted signal for a word line, coupled to a word line driving signal line for transmitting a voltage signal to the word line, coupled to a first power supply, and coupled to a second power supply for providing a voltage higher than the voltage of the first power supply, can supply a compensating voltage for the word line from the second power supply through the word line driving signal line when a voltage of the word line is decreased.

Abstract: A semiconductor integrated circuit having a power supply terminal, ground terminal and a substrate bias terminal comprises a substrate voltage generating circuit connected to the power supply terminal and the ground terminal for generating a substrate bias voltage of a predetermined value and for applying the same to the substrate bias terminal, a MOS transistor provided between the substrate bias terminal and the ground terminal for bringing the substrate potential to the ground potential when the supply voltage of the power supply terminal exceeds a prescribed voltage value and a plurality of diode connected MOS transistors connected between the power supply terminal and the gate of the MOS transistor for deciding the prescribed voltage value.

Abstract: A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.

Abstract: A memory cell array is divided into four blocks #1 to #4. The blocks #1 and #3 are operated when a row address signal RA.sub.8 equals "0". The blocks #2 and #4 are operated when the row address signal RA.sub.8 equals "1". A spare row sub-decoder is provided in each of the blocks. Spare row sub-decoders in the blocks #1 and #2 are connected to a spare row main decoder through a single spare decoder selecting line. The spare row sub-decoders in the blocks #2 and #4 are connected to the other spare row main decoder through another spare decoder selecting line. The spare main decoders are responsive to the row address signal RA.sub.8 and row address signals RA.sub.2, RA.sub.2, . . . , RA.sub.7, RA.sub.7 for operating a spare row sub-decoder in a block which is in the operating state.

Abstract: A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.

Abstract: A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.