Patents by Inventor Hideshi Nishikawa
Hideshi Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7397110Abstract: A high-resistance silicon wafer is manufactured in which a gettering ability, mechanical strength, and economical efficiency are excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is implemented on the side of a device maker. A heat treatment for forming an oxygen precipitate nucleus is performed at 500 to 900° C. for 5 hours or more in a non-oxidizing atmosphere and a heat treatment for growing an oxygen precipitate is performed at 950 to 1050° C. for 10 hours or more on a high-oxygen and carbon-doped high-resistance silicon wafer in which resistivity is 100 ?cm or more, an oxygen concentration is 14×1017 atoms/cm3 (ASTM F-121, 1979) or more and a carbon concentration is 0.5×1016 atoms/cm3 or more. By these heat treatments, a remaining oxygen concentration in the wafer is controlled to be 12×1017 atoms/cm3 (ASTM F-121, 1979) or less.Type: GrantFiled: April 16, 2003Date of Patent: July 8, 2008Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Nobumitsu Takase, Hideshi Nishikawa, Makoto Ito, Koji Sueoka, Shinsuke Sadamitsu
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Patent number: 7273647Abstract: A silicon annealed wafer having a sufficient thick layer free from COP defects on the surface, and a sufficient uniform BMD density in the inside can be produced by annealing either a base material wafer having nitrogen at a concentration of less than 1×1014 atoms/cm3, COP defects having a size of 0.1 ?m or less in the highest frequency of occurrence and no COP defects having a size of 0.2 ?m or more, oxygen precipitates at a density of 1×104 counts/cm2 or more, and BMDs (oxygen precipitates), where the ratio of the maximum to the minimum of the BMD density in the radial direction of the wafer is 3 or less, or a base material wafer grown at specific average temperature gradients within specific temperature ranges and specific cooling times for a single crystal at a nitrogen concentration of less than 1×1014 atoms/cm3, employing the Czochralski method.Type: GrantFiled: March 26, 2004Date of Patent: September 25, 2007Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Hideshi Nishikawa, Nobumitsu Takase, Kazuyuki Egashira, Hiroshi Hayakawa
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Patent number: 7220308Abstract: To suppress a fluctuation in resistivity around a target value to thereby stably manufacture high resistivity silicon single crystals having almost the same resistivity values in a manufacturing method wherein a silicon raw material is molten to manufacture a high resistivity silicon single crystal in the range of from 100 to 2000 ? cm with a CZ method. In a case where poly-silicon produced with a Siemens method using trichlorosilane as raw material is used as the silicon raw material, an impurity concentration in the silicon raw material is selected so as to be controlled in the range of from ?5 to 50 ppta method in terms of (a donor concentration—an acceptor concentration) and the selected poly-silicon is used. In a case of a MCZ method, the poly-silicon is selected in the range of from ?25 to 20 ppta and the selected poly-silicon is used. Instead of the raw material, poly-silicon produced with a Siemens method using monosilane as raw material is used.Type: GrantFiled: April 21, 2004Date of Patent: May 22, 2007Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Nobumitsu Takase, Hideshi Nishikawa, Makoto Ito, Koujl Sueoka, Shinsuke Sadamitsu
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Patent number: 7014704Abstract: A method for growing a silicon single crystal used for semiconductor integrated circuit devices, wherein the single crystal is grown by the CZ method at a nitrogen concentration of 1×1013 atoms/cm3–1×1015 atoms/cm3 with a cooling rate of not less than 2.5° C./min at a crystal temperature of 1150° C.–1000° C., in which case, the pulling rate is adjusted such that the outside diameter of a circular region including oxidation-induced stacking faults generated at the center of a wafer which is subjected to the oxidation heat treatment at high temperature is not more than ? of the wafer diameter, wherein the wafer is prepared by slicing the grown single crystal. In the growth method, the concentration of oxygen in the silicon single crystal is preferably not more than 9×1017 atoms/cm3 (ASTM '79). With this method, the silicon single crystal, in which the generation of Grown-in defects can be effectively suppressed, can be produced in a simple process without any increase in the production cost.Type: GrantFiled: June 6, 2003Date of Patent: March 21, 2006Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toshiaki Ono, Tadami Tanaka, Shigeru Umeno, Eiichi Asayama, Hideshi Nishikawa
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Publication number: 20050253221Abstract: A high-resistance silicon wafer is manufactured in which a gettering ability, mechanical strength, and economical efficiency are excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is implemented on the side of a device maker. A heat treatment for forming an oxygen precipitate nucleus is performed at 500 to 900° C. for 5 hours or more in a non-oxidizing atmosphere and a heat treatment for growing an oxygen precipitate is performed at 950 to 1050° C. for 10 hours or more on a high-oxygen and carbon-doped high-resistance silicon wafer in which resistivity is 100 ?cm or more, an oxygen concentration is 14×1017 atoms/cm3 (ASTM F-121, 1979) or more and a carbon concentration is 0.5×1016 atoms/cm3 or more. By these heat treatments, a remaining oxygen concentration in the wafer is controlled to be 12×1017 atoms/cm3 (ASTM F-121, 1979) or less.Type: ApplicationFiled: April 16, 2003Publication date: November 17, 2005Applicant: SUMITOMO MITSUBISHI SILICON CORPORATIONInventors: Nobumitsu Takase, Hideshi Nishikawa, Makoto Ito, Koji Sueoka, Shinsuke Sadamitsu
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Publication number: 20050000410Abstract: To suppress a fluctuation in resistivity around a target value to thereby stably manufacture high resistivity silicon single crystals having almost the same resistivity values in a manufacturing method wherein a silicon raw material is molten to manufacture a high resistivity silicon single crystal in the range of from 100 to 2000 ? cm with a CZ method. In a case where poly-silicon produced with a Siemens method using trichlorosilane as raw material is used as the silicon raw material, an impurity concentration in the silicon raw material is selected so as to be controlled in the range of from ?5 to 50 ppta method in terms of (a donor concentration—an acceptor concentration) and the selected poly-silicon is used. In a case of a MCZ method, the poly-silicon is selected in the range of from ?25 to 20 ppta and the selected poly-silicon is used. Instead of the raw material, poly-silicon produced with a Siemens method using monosilane as raw material is used.Type: ApplicationFiled: April 21, 2004Publication date: January 6, 2005Inventors: Nobumitsu Takase, Hideshi Nishikawa, Makoto Ito, Kouji Sueoka, Shinsuke Sadamitsu
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Patent number: 6835245Abstract: Epitaxial wafers showing marked IG effects can be manufactured from silicon single crystals doped or not doped with nitrogen without requiring any additional heat treatment process step while reducing the density of epitaxial layer defects. According to the first manufacturing method, an epitaxial layer is allowed to grow on the surface of a wafer sliced from a single crystal produced by employing a cooling rate of not less than 7.3° C./min in the temperature range of 1200-1050° C. in the step of pulling up thereof. According to the second manufacturing method, an epitaxial layer is allowed to grow on the surface of a silicon wafer sliced from a silicon single crystal doped with 1×1012 atoms/cm3 to 1×1014 atoms/cm3 as produced by employing a cooling rate of not less than 2.7° C./min in the temperature range of 1150-1020° C. and then a cooling rate of not more than 1.2° C./min in the temperature range of 1000-850° C. in the step of pulling up thereof.Type: GrantFiled: June 20, 2001Date of Patent: December 28, 2004Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toshiaki Ono, Tadami Tanaka, Eiichi Asayama, Hideshi Nishikawa, Masataka Horai
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Publication number: 20040244674Abstract: A method for growing a silicon single crystal used for semiconductor integrated circuit devices, wherein the single crystal is grown by the CZ method at a nitrogen concentration of 1×1013 atoms/cm3-1×1015 atoms/cm3 with a cooling rate of not less than 2.5° C./min at a crystal temperature of 1150° C.-1000° C., in which case, the pulling rate is adjusted such that the outside diameter of a circular region including oxidation-induced stacking faults generated at the center of a wafer which is subjected to the oxidation heat treatment at high temperature is not more than ⅗ of the wafer diameter, wherein the wafer is prepared by slicing the grown single crystal. In the growth method, the concentration of oxygen in the silicon single crystal is preferably not more than 9×1017 atoms/cm3 (ASTM '79).Type: ApplicationFiled: June 6, 2003Publication date: December 9, 2004Inventors: Toshiaki Ono, Tadami Tanaka, Shigeru Umeno, Eiichi Asayama, Hideshi Nishikawa
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Publication number: 20040194692Abstract: A silicon annealed wafer having a sufficient thick layer free from COP defects on the surface, and a sufficient uniform BMD density in the inside can be produced by annealing either a base material wafer having nitrogen at a concentration of less than 1×1014 atoms/cm3, COP defects having a size of 0.1 &mgr;m or less in the highest frequency of occurrence and no COP defects having a size of 0.2 &mgr;m or more, oxygen precipitates at a density of 1×104 counts/cm2 or more, and BMDs (oxygen precipitates), where the ratio of the maximum to the minimum of the BMD density in the radial direction of the wafer is 3 or less, or a base material wafer grown at specific average temperature gradients within specific temperature ranges and specific cooling times for a single crystal at a nitrogen concentration of less than 1×1014 atoms/cm3, employing the Czochralski method.Type: ApplicationFiled: March 26, 2004Publication date: October 7, 2004Inventors: Hideshi Nishikawa, Nobumitsu Takase, Kazuyuki Egashira, Hiroshi Hayakawa
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Patent number: 6709957Abstract: The invention relates to a method of producing epitaxial wafers for the manufacture of high integration density devices capable of showing stable gettering effect. Specifically, it provides (1) a method of producing epitaxial wafers which comprises subjecting a silicon wafer sliced from a single crystal ingot grown by doping with not less than 1×1013 atoms/cm3 of nitrogen to 15 minutes to 4 hours of heat treatment at a temperature not lower than 700° C. but lower than 900° C. and then to epitaxial growth treatment. It is desirable that the above single crystal ingot have an oxygen concentration of not less than 11×1017 atoms/cm3. Further, (2) the above heat treatment is desirably carried out prior to the step of mirror polishing of silicon wafers. Furthermore, (3) it is desirable that the pulling rate be not increased in starting tail formation as compared with the pulling rate of the body in growing the above single crystal ingot.Type: GrantFiled: June 18, 2002Date of Patent: March 23, 2004Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Eiichi Asayama, Yasuo Koike, Tadami Tanaka, Toshiaki Ono, Masataka Horai, Hideshi Nishikawa
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Publication number: 20030008447Abstract: The invention relates to a method of producing epitaxial wafers for the manufacture of high integration density devices capable of showing stable gettering effect. Specifically, it provides (1) a method of producing epitaxial wafers which comprises subjecting a silicon wafer sliced from a single crystal ingot grown by doping with not less than 1×1013 at ms/cm3 of nitrogen to 15 minutes to 4 hours of heat treatment at a temperature not lower than 700° C. but lower than 900° C. and then to epitaxial growth treatment. It is desirable that the above single crystal ingot have an oxygen concentration of not less than 11×1017 atoms/cm3. Further, (2) the above heat treatment is desirably carried out prior to the step of mirror polishing of silicon wafers. Furthermore, (3) it is desirable that the pulling rate be not increased in starting tail formation as compared with the pulling rate of the body in growing the above single crystal ingot.Type: ApplicationFiled: June 18, 2002Publication date: January 9, 2003Inventors: Eiichi Asayama, Yasuo Koike, Tadami Tanaka, Toshiaki Ono, Masataka Horai, Hideshi Nishikawa
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Publication number: 20020017234Abstract: Epitaxial wafers showing marked IG effects can be manufactured from silicon single crystals doped or not doped with nitrogen without requiring any additional heat treatment process step while reducing the density of epitaxial layer defects. According to the first manufacturing method, an epitaxial layer is allowed to grow on the surface of a wafer sliced from a single crystal produced by employing a cooling rate of not less than 7.3° C./min in the temperature range of 1200-1050° C. in the step of pulling up thereof. According to the second manufacturing method, an epitaxial layer is allowed to grow on the surface of a silicon wafer sliced from a silicon single crystal doped with 1×1012 atoms/cm3 to 1×1014 atoms/cm3 as produced by employing a cooling rate of not less than 2.7° C./min in the temperature range of 1150-1020° C. and then a cooling rate of not more than 1.2° C./min in the temperature range of 1000-850° C. in the step of pulling up thereof.Type: ApplicationFiled: June 20, 2001Publication date: February 14, 2002Applicant: Sumitomo Metal Industries, Ltd., Osaka-shi, JapanInventors: Toshiaki Ono, Tadami Tanaka, Eiichi Asayama, Hideshi Nishikawa, Masataka Horai
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Patent number: 6337219Abstract: A method of manufacturing a silicon single crystal to be grown by the Czochralski method, wherein a crystal is pulled up in a CZ furnace by changing an average pulling rate for a crystal, having a predetermined length, a plurality of times, a relation between the average pulling rate and the OSF ring diameter for each pulling length is examined, an average pulling rate pattern for generation or disappearance of an OSF ring at a predetermined position is designed based on the examined results, and the single crystal is grown according to the average pulling rate pattern, and a silicon wafer not having grown-in defects is manufactured.Type: GrantFiled: December 20, 1999Date of Patent: January 8, 2002Assignee: Sumitomo Metal Industries, Ltd.Inventor: Hideshi Nishikawa
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Patent number: 5508207Abstract: The present invention provides a method of manufacturing a semiconductor wafer whereby (1) deterioration of a micro-roughness in a low temperature range in hydrogen atmospheric treatment and increase of resistivity due to outward diffusion of an electrically active impurity in a high temperature range are prevented; (2) in the heat treatment in a hydrogen gas atmosphere, the concentration of gas molecules in the atmosphere, such as water, oxygen and the like, are brought to 5 ppm or less in water molecule conversion; and a reaction is suppressed in which a substrate surface is oxidized unequally and the micro-roughness deteriorates; and (3) the same kind of impurity as the electrically active impurity contained in a Si substrate is mixed into the atmosphere and the outward diffusion of the impurity in the vicinity of the Si substrate surface is prevented to prevent variation of the resistivity.Type: GrantFiled: April 26, 1994Date of Patent: April 16, 1996Assignee: Sumitomo Sitix CorporationInventors: Masataka Horai, Naoshi Adachi, Hideshi Nishikawa, Masakazu Sano