Patents by Inventor Hideshi Yamada
Hideshi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110109625Abstract: A drawing processing apparatus for performing tessellation processing, comprising a pixel shader and a texture unit. An internal division operation part of the pixel shader issues texture load instructions to the texture unit, specifying parametric coordinate values of a patch of a parametric surface, and thereby acquires internal division factors interpolated based on the parametric coordinate values from the texture unit. The internal division operation part issues texture load instructions to the texture unit further, specifying the internal division factors acquired from the texture unit as new interpolation factors, and thereby acquires control points internally divided based on the internal division factors in advance from the texture unit.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Applicant: SONY COMPUTER ENTERTAINMENT INC.Inventor: Hideshi Yamada
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Publication number: 20110072464Abstract: An apparatus and method capable of selecting and providing content while reducing the load on a user are provided. A controlled device is determined based on content identification information. Control information corresponding to the determined controlled device is generated and output to, for example, a remote controller, and device control is performed based on a control signal from the remote controller. The user can output and view content without performing processing necessary to output the content, such as processing on a control device, a channel operation to the control device, and searching for the content storage location. Further, content cards recording content information are displayed as a card group and content information of a card at a position of a cursor is displayed.Type: ApplicationFiled: September 16, 2010Publication date: March 24, 2011Applicant: SONY CORPORATIONInventors: Osamu Watanabe, Tetsugo Inada, Hideshi Yamada, Yasuhiro Moriyama
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Patent number: 7903112Abstract: A drawing processing apparatus for performing tessellation processing, comprising a pixel shader and a texture unit. An internal division operation part of the pixel shader issues texture load instructions to the texture unit, specifying parametric coordinate values of a patch of a parametric surface, and thereby acquires internal division factors interpolated based on the parametric coordinate values from the texture unit. The internal division operation part issues texture load instructions to the texture unit further, specifying the internal division factors acquired from the texture unit as new interpolation factors, and thereby acquires control points internally divided based on the internal division factors in advance from the texture unit.Type: GrantFiled: April 16, 2010Date of Patent: March 8, 2011Assignee: Sony Computer Entertainment, Inc.Inventor: Hideshi Yamada
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Publication number: 20110050685Abstract: An image processing apparatus, which creates a pseudo three-dimensional image that improves depth perception of the image, includes: an input image acquiring unit that acquires an input image and a binary mask image that specifies an object area on the input image; a combining unit that extracts pixels in an area inside a quadrangular frame picture of the input image and pixels in the object area, specified by the binary mask image, on the input image to create a combined image; and a frame picture combining position determining unit that determines a position on the combined image at which the quadrangular frame picture is placed so that one of a pair of opposite edges of the quadrangular frame picture includes an intersection with boundary of the object area and another of the pair does not include an intersection with the boundary of the object area.Type: ApplicationFiled: August 18, 2010Publication date: March 3, 2011Inventor: Hideshi YAMADA
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Publication number: 20110029469Abstract: An information processing apparatus, which performs setting of a mixture model function representing a mixture model along with adaptively adjusting the number of model components mixed in the mixture model, includes an acquisition section configured to acquire a first data sample and a second data sample, both of which are composed of multi-dimensions; a mixture-model-function generation section configured to generate a mixture model function on the basis of the first data sample; a mixture-model-function goodness-of-fit calculation section configured to calculate a goodness of fit for the mixture model function on the basis of the second data sample; and a mixture-model-function update section configured to update the mixture model function so as to adjust the number of model components mixed in a mixture model, which are represented by the mixture model function, on the basis of the goodness of fit for the mixture model function.Type: ApplicationFiled: July 29, 2010Publication date: February 3, 2011Inventor: Hideshi YAMADA
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Publication number: 20100214295Abstract: A drawing processing apparatus for performing tessellation processing, comprising a pixel shader and a texture unit. An internal division operation part of the pixel shader issues texture load instructions to the texture unit, specifying parametric coordinate values of a patch of a parametric surface, and thereby acquires internal division factors interpolated based on the parametric coordinate values from the texture unit. The internal division operation part issues texture load instructions to the texture unit further, specifying the internal division factors acquired from the texture unit as new interpolation factors, and thereby acquires control points internally divided based on the internal division factors in advance from the texture unit.Type: ApplicationFiled: April 16, 2010Publication date: August 26, 2010Applicant: SONY COMPUTER ENTERTAINMENT INC.Inventor: Hideshi Yamada
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Patent number: 7746342Abstract: A drawing processing apparatus for performing tessellation processing, comprising a pixel shader and a texture unit. An internal division operation part of the pixel shader issues texture load instructions to the texture unit, specifying parametric coordinate values of a patch of a parametric surface, and thereby acquires internal division factors interpolated based on the parametric coordinate values from the texture unit. The internal division operation part issues texture load instructions to the texture unit further, specifying the internal division factors acquired from the texture unit as new interpolation factors, and thereby acquires control points internally divided based on the internal division factors in advance from the texture unit.Type: GrantFiled: February 23, 2006Date of Patent: June 29, 2010Assignee: Sony Computer Entertainment Inc.Inventor: Hideshi Yamada
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Publication number: 20100061658Abstract: An image processing apparatus generates a 3-value image from a 2-value image, wherein the first and second values from the 2-value image indicate foreground and background regions of an input image, and the third value indicates an unknown region of predetermined width at the boundary therebetween. A ratio image is generated from the input image and the 3-value image, having a fourth value indicating the ratio of the first value. The 3-value image is updated by defining a predetermined range near a pixel in the 3-value image corresponding to a pixel in the ratio image whose fourth value is greater than a minimum value and less than a maximum value, and then sets all pixels within the defined range to the third value. If the updated 3-value image is determined to be identical or nearly identical to the pre-update 3-value image, then the updated 3-value image is output.Type: ApplicationFiled: September 4, 2009Publication date: March 11, 2010Inventor: Hideshi Yamada
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Publication number: 20100061628Abstract: An image processing apparatus includes a defined binary image generating unit configured to generate a defined binary image associated with a level image, which is associated with an input image, the level image having pixel values of pixels represented using a first value, by regarding a pixel as a defined or undefined region pixel and setting the pixel to have a predetermined second or third value; and an estimated foreground color image generation unit configured to generate an estimated foreground color image associated with the input image, by setting the pixel values of the pixels regarded as the undefined region pixels in the defined binary image to pixel values of pixels in the input image corresponding to pixels for which distances each obtained from an integrated value of the amounts of change in continuity information are shortest from among the pixels that are regarded as the defined region pixels.Type: ApplicationFiled: September 1, 2009Publication date: March 11, 2010Inventor: Hideshi YAMADA
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Patent number: 7475210Abstract: An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit determination sections determine that the data stored in the allocated addresses does not exist in the corresponding cache memories, request issuing sections issue transfer requests for the data from the main memory to the cache memories, to a request arbitration section. The request arbitration section transmits the transfer requests to the main memory with priority given to data of greater sizes to transfer. The main memory transfers data to the cache memories in accordance with the transfer requests. A data synchronization section reads a plurality of read units of data from a plurality of cache memories, and generates a data stream for output by a stream sending section.Type: GrantFiled: December 19, 2005Date of Patent: January 6, 2009Assignee: Sony Computer Entertainment Inc.Inventor: Hideshi Yamada
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Publication number: 20080301681Abstract: An information processing apparatus including: a plurality of data processing functional blocks each used for carrying out individual data processing; a flow control section configured to execute control of data flows among the data processing functional blocks; and a control section configured to carry out a setting process to set the data processing functional blocks and the flow control section. The control section acquires configuration information in accordance with a task list for data processing to be carried out; carries out the setting process to set the data processing functional blocks and the flow control section on the basis of the acquired configuration information; and constructs a data processing configuration adapted to various kinds of data processing to be carried out.Type: ApplicationFiled: May 30, 2008Publication date: December 4, 2008Inventors: Junichi Sakamoto, Masaharu Yoshimori, Tanio Nagasaki, Shinsuke Koyama, Kazumasa Ito, Minoru Takahata, Mikako Hatakenaka, Jin Satoh, Hideshi Yamada, Kenichiro Yokota, Hideki Takeuchi, Hitoshi Ishikawa
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Patent number: 7280121Abstract: An image processing apparatus capable of realizing accurate anti-aliasing with a small memory, without being affected by the order of drawing, and without inducing a drop in the drawing speed, including an anti-aliasing system obtaining edge information from an image after drawing, determining a processing content necessary for the anti-aliasing, and performing the determined processing. Specifically, either of the information of a z-buffer and the information of the normal vector at each pixel obtained at the time of drawing, or both information, is scanned or by the information of normal vectors restored from the information of the z-buffer is used, a state machine for holding the state and a counter for measuring the continuity of an edge are prescribed, the value of which pixel adjacent in which direction to each pixel on each edge and what kind of ratio to use for blending are determined, and the determined values are used for blending. This is performed successively until the pixel values are updated.Type: GrantFiled: September 23, 2004Date of Patent: October 9, 2007Assignee: Sony CorporationInventors: Teruyuki Nakahashi, Osamu Watanabe, Tanio Nagasaki, Tetsugo Inada, Yasuhiro Moriyama, Hideshi Yamada
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Publication number: 20060197760Abstract: A drawing processing apparatus for performing tessellation processing, comprising a pixel shader and a texture unit. An internal division operation part of the pixel shader issues texture load instructions to the texture unit, specifying parametric coordinate values of a patch of a parametric surface, and thereby acquires internal division factors interpolated based on the parametric coordinate values from the texture unit. The internal division operation part issues texture load instructions to the texture unit further, specifying the internal division factors acquired from the texture unit as new interpolation factors, and thereby acquires control points internally divided based on the internal division factors in advance from the texture unit.Type: ApplicationFiled: February 23, 2006Publication date: September 7, 2006Inventor: Hideshi Yamada
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Publication number: 20060184737Abstract: An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit determination sections determine that the data stored in the allocated addresses does not exist in the corresponding cache memories, request issuing sections issue transfer requests for the data from the main memory to the cache memories, to a request arbitration section. The request arbitration section transmits the transfer requests to the main memory with priority given to data of greater sizes to transfer. The main memory transfers data to the cache memories in accordance with the transfer requests. A data synchronization section reads a plurality of read units of data from a plurality of cache memories, and generates a data stream for output by a stream sending section.Type: ApplicationFiled: December 19, 2005Publication date: August 17, 2006Inventor: Hideshi Yamada
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Patent number: 6889495Abstract: The present invention provides a gas turbine combustor which makes it possible to achieve both a high combustion efficiency and low NOx emissions characteristics over a wide output power range without using a device that can vary the flow rate of the air used for combustion, by burning a lean mixture using high-temperature burned gas. The gas turbine combustor 10 comprises pre-mixture injection tubes 16 which conduct a mixture of fuel and air into a combustion chamber 11. The mixture from the pre-mixture injection tubes 16 is injected toward burned gas 19a present on the downstream side of the flame 19, which is injected from burners 15 that open into the combustion chamber 11, and this mixture is mixed with the burned gas 19a. Even in a mixture which is leaner than the lower limit of inflammability, the radicals in the burned gas 19a are effective in initiating reactions, so that the combustion of the mixture can be started.Type: GrantFiled: March 7, 2003Date of Patent: May 10, 2005Assignee: National Aerospace Laboratory of JapanInventors: Shigeru Hayashi, Hideshi Yamada
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Publication number: 20050068326Abstract: An image processing apparatus capable of extracting edge information accurate enough to be able to be utilized for anti-aliasing without rendering of pixels other than the originally necessary drawn pixels and without inducing a drop in the drawing speed, including an anti-aliasing system for restoring edge information for an x-direction and a y-direction in screen coordinates from an image after drawing, determining a processing content necessary for the anti-aliasing from the obtained edge information, and performing the determined processing. Specifically, by scanning either of the information of a z-buffer and the information of the normal vector at each pixel obtained at the time of drawing, or both information, or by using the information of normal vectors restored from the information of the z-buffer, the anti-aliasing is applied to each pixel.Type: ApplicationFiled: September 23, 2004Publication date: March 31, 2005Inventors: Teruyuki Nakahashi, Osamu Watanabe, Tanio Nagasaki, Tetsugo Inada, Yasuhiro Moriyama, Hideshi Yamada
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Publication number: 20050068333Abstract: An image processing apparatus capable of realizing accurate anti-aliasing with a small memory, without being affected by the order of drawing, and without inducing a drop in the drawing speed, including an anti-aliasing system obtaining edge information from an image after drawing, determining a processing content necessary for the anti-aliasing, and performing the determined processing. Specifically, either of the information of a z-buffer and the information of the normal vector at each pixel obtained at the time of drawing, or both information, is scanned or by the information of normal vectors restored from the information of the z-buffer is used, a state machine for holding the state and a counter for measuring the continuity of an edge are prescribed, the value of which pixel adjacent in which direction to each pixel on each edge and what kind of ratio to use for blending are determined, and the determined values are used for blending. This is performed successively until the pixel values are updated.Type: ApplicationFiled: September 23, 2004Publication date: March 31, 2005Inventors: Teruyuki Nakahashi, Osamu Watanabe, Tanio Nagasaki, Tetsugo Inada, Yasuhiro Moriyama, Hideshi Yamada
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Publication number: 20030167771Abstract: The present invention provides a gas turbine combustor which makes it possible to achieve both a high combustion efficiency and low NOx emissions characteristics over a wide output power range without using a device that can vary the flow rate of the air used for combustion, by burning a lean mixture using high-temperature burned gas. The gas turbine combustor 10 comprises pre-mixture injection tubes 16 which conduct a mixture of fuel and air into a combustion chamber 11. The mixture from the pre-mixture injection tubes 16 is injected toward burned gas 19a present on the downstream side of the flame 19, which is injected from burners 15 that open into the combustion chamber 11, and this mixture is mixed with the burned gas 19a. Even in a mixture which is leaner than the lower limit of inflammability, the radicals in the burned gas 19a are effective in initiating reactions, so that the combustion of the mixture can be started.Type: ApplicationFiled: March 7, 2003Publication date: September 11, 2003Applicant: NATIONAL AEROSPACE LABORATORY OF JAPANInventors: Shigeru Hayashi, Hideshi Yamada
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Patent number: 5172299Abstract: A multilayer capacitor in which a plurality of inner electrodes are laminated while being separated by dielectric layers in a dielectric body, each of the inner electrodes having a plurality of inner electrode fingers formed while being separated by gaps, and respective ones of the plurality of inner electrode fingers having at least two different widths.Type: GrantFiled: April 19, 1991Date of Patent: December 15, 1992Assignee: Murata Manufacturing Co., Inc.Inventors: Hideshi Yamada, Noboru Kato