Patents by Inventor Hidetaka Tsuji
Hidetaka Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10431322Abstract: According to one embodiment, a first string is coupled to the bit line via a first transistor and includes a first cell transistor. A second string is coupled to the bit line via a second transistor and includes a second cell transistor. The first and second cell transistors are coupled to the word line. A controller is configured to instruct the memory device to write first data to the first cell transistor and to write second data to the second cell transistor. The controller is further configured to instruct the memory device to read data from the first cell transistor while storing the first data and the second data after making the instruction for writing the first data and the second data.Type: GrantFiled: July 31, 2018Date of Patent: October 1, 2019Assignee: Toshiba Memory CorporationInventors: Hiroki Nishida, Hidetaka Tsuji, Tomoyuki Kantani
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Publication number: 20190287642Abstract: According to one embodiment, a first string is coupled to the bit line via a first transistor and includes a first cell transistor. A second string is coupled to the bit line via a second transistor and includes a second cell transistor. The first and second cell transistors are coupled to the word line. A controller is configured to instruct the memory device to write first data to the first cell transistor and to write second data to the second cell transistor. The controller is further configured to instruct the memory device to read data from the first cell transistor while storing the first data and the second data after making the instruction for writing the first data and the second data.Type: ApplicationFiled: July 31, 2018Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Hiroki Nishida, Hidetaka Tsuji, Tomoyuki Kantani
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Patent number: 9653156Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.Type: GrantFiled: May 14, 2015Date of Patent: May 16, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masanobu Shirakawa, Tsuyoshi Atsumi, Hidetaka Tsuji, Tomoyuki Kantani, Hideaki Yamamoto, Yasuhiko Kurosawa
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Publication number: 20160247561Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.Type: ApplicationFiled: May 14, 2015Publication date: August 25, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masanobu SHIRAKAWA, Tsuyoshi Atsumi, Hidetaka Tsuji, Tomoyuki Kantani, Hideaki Yamamoto, Yasuhiko Kurosawa
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Patent number: 9229851Abstract: A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.Type: GrantFiled: September 1, 2009Date of Patent: January 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Sukegawa, Hidetaka Tsuji, Shuji Takano
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Patent number: 9142300Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a storage area having a plurality of memory cells configured to store data. The control circuit determines whether data write to the storage area is possible or impossible.Type: GrantFiled: December 12, 2013Date of Patent: September 22, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroki Tagawa, Hidetaka Tsuji
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Patent number: 9081664Abstract: According to one embodiment, a memory system includes a memory unit, a first controller, and a second controller. In the memory unit, first to fourth levels (first level<second level<third level<fourth level) are written based on first and second data. The first controller comprises a first write mode of writing the fourth level based on the data of the second page and then writing the second and third levels and a second write mode of writing the third and fourth levels and then writing the second level. The second controller issues at least one of second and third commands to be supplied to the first controller in order to select at least one of the first and second write modes.Type: GrantFiled: November 27, 2012Date of Patent: July 14, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Shingo Tanimoto, Hidetaka Tsuji
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Patent number: 9058254Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.Type: GrantFiled: February 7, 2012Date of Patent: June 16, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Takafumi Ito, Hidetaka Tsuji
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Patent number: 9043679Abstract: A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.Type: GrantFiled: December 19, 2012Date of Patent: May 26, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hitoshi Shiga, Hidetaka Tsuji
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Publication number: 20150063034Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a storage area having a plurality of memory cells configured to store data. The control circuit determines whether data write to the storage area is possible or impossible.Type: ApplicationFiled: December 12, 2013Publication date: March 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroki TAGAWA, Hidetaka TSUJI
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Patent number: 8797821Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.Type: GrantFiled: July 16, 2012Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Hidetaka Tsuji
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Publication number: 20140047162Abstract: According to one embodiment, a memory system includes a memory unit, a first controller, and a second controller. In the memory unit, first to fourth levels (first level<second level<third level<fourth level) are written based on first and second data. The first controller comprises a first write mode of writing the fourth level based on the data of the second page and then writing the second and third levels and a second write mode of writing the third and fourth levels and then writing the second level. The second controller issues at least one of second and third commands to be supplied to the first controller in order to select at least one of the first and second write modes.Type: ApplicationFiled: November 27, 2012Publication date: February 13, 2014Inventors: Shingo TANIMOTO, Hidetaka Tsuji
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Publication number: 20140006906Abstract: A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.Type: ApplicationFiled: December 19, 2012Publication date: January 2, 2014Inventors: Hitoshi Shiga, Hidetaka Tsuji
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Patent number: 8356134Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.Type: GrantFiled: December 13, 2007Date of Patent: January 15, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takafumi Ito, Hidetaka Tsuji
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Patent number: 8327063Abstract: A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device.Type: GrantFiled: March 17, 2009Date of Patent: December 4, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Shiga, Hidetaka Tsuji
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Publication number: 20120281473Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.Type: ApplicationFiled: July 16, 2012Publication date: November 8, 2012Inventor: Hidetaka TSUJI
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Patent number: 8243545Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.Type: GrantFiled: July 26, 2011Date of Patent: August 14, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Hidetaka Tsuji
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Publication number: 20120137057Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.Type: ApplicationFiled: February 7, 2012Publication date: May 31, 2012Inventors: Takafumi Ito, Hidetaka Tsuji
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Patent number: 8145827Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.Type: GrantFiled: December 13, 2007Date of Patent: March 27, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takafumi Ito, Hidetaka Tsuji
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Patent number: 8098523Abstract: A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M?2i, where i is a natural number and M is a natural number greater than or equal to 3) of data. The memory block includes the first memory cell transistors and is erase unit of the data. The data held in the first memory cell transistors included in the memory block is erased simultaneously. The size of data the memory block is capable of holding is L bits (L=2k, where k is a natural number). The word lines connect in common the control gates of the first memory cell transistors.Type: GrantFiled: July 7, 2010Date of Patent: January 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hidetaka Tsuji, Tomoji Takada