Patents by Inventor Hidetomo IWAGAWA

Hidetomo IWAGAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220405594
    Abstract: An analysis unit (110) analyzes a composition of a neural network composed of a plurality of layers and acquires a layer parameter (210) indicating an attribute of each of the plurality of layers. A conversion unit (120) converts the layer parameter (210) in such a way that processing performance of a circuit which executes an operation of the neural network does not deteriorate and a computation amount of the neural network increases. The conversion unit (120) increases the computation amount by treating the numbers of input/output edges in each of the plurality of layers as the layer parameter and increasing the numbers of input/output edges.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 22, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryo YAMAMOTO, Hidetomo IWAGAWA
  • Publication number: 20220309351
    Abstract: A processing time calculation unit (221) calculates, based on performance information (32) on a computing unit in which a neural network is implemented, processing time to be taken for processing by the neural network in case where the neural network is implemented in the computing unit. An attainment determination unit (23) determines whether the calculated processing time is longer than required time or not. A structure transformation unit (225) transforms a structure of the neural network in case where it is determined that the processing time is longer than the required time and refrains from transforming the structure of the neural network in case where it is determined that the processing time is equal to or shorter than the required time.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shunsuke TATSUMI, Ryo YAMAMOTO, Hidetomo IWAGAWA
  • Publication number: 20210350216
    Abstract: A reception unit (110) receives NN information (151) and non-functional requirements (152) demanded for a circuit. A search unit (120) generates combinations of interlayer architectures and intra-layer architectures as architecture combinations (121). Then, the search unit (120) searches for a plurality of architecture combination candidates (122) that reduce an amount of delay as the non-functional requirements, from among the architecture combinations (121). A determination unit (130) determines whether each of the plurality of architecture combination candidates (122) satisfies the non-functional requirements (152) or not. A candidate information generation unit (140) generates candidate information (154) including architecture candidates (131) that satisfy the non-functional requirements among the plurality of architecture combination candidates (122).
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryo YAMAMOTO, Hidetomo IWAGAWA