Abstract: A UE includes an EUTRA-CMR reception unit that receives a codec mode request (EUTRA-CMR) including a codec mode that is determined by an eNB in accordance with a radio condition of the UE, a mode switching notification unit that notifies an encoder of switching to the codec mode included in the received codec mode request; and a mode switching acknowledgement unit that transmits a response message to the eNB when confirming that the encoder switches the codec mode.

Abstract: A radio communication system and the method thereof which can eliminate influence of atmospheric interference or an interference signal having a strong signal level and which can allow repeater transmission without difficulty. A plurality of repeater stations are located between an upper station and a lower station, and each repeater station transmits a TDMA signal whose received signal level exceeds a reference value transmitted from the lower station to the upper station. The upper station generates usage state information for respective time slots of the received TDMA signal, and transmits the usage state information to each repeater station. Each repeater station determines whether or not the corresponding time slot of the TDMA signal to be repeated is used in accordance with the usage state information received from the upper station and, if the time slot is unused, the repeater transmission to the corresponding time slot is allowed.

Abstract: A phase-locked loop circuit includes a voltage-controlled oscillator, a pre-scaler, a main counter, a shift register, and a phase comparison section. The oscillation frequency of the voltage-controlled oscillator is controlled on the basis of phase different information. The pre-scaler frequency-divides an oscillation frequency output from the voltage-controlled oscillator by one of frequency division ratios of 1/j (j is a positive integer) and 1/(j+1) which is selected in accordance with an external control signal. The main counter frequency-divides a frequency division output from the pre-scaler by a frequency division ratio of n (n is a positive integer). The shift register generates .alpha. (.alpha. is an integer equal to or larger than two) time series pulse strings which are synchronized with the output from the pre-scaler and have phases sequentially delayed by one period on the basis of a frequency division output from the main counter.

Abstract: To provide stable oscillation frequencies at small step intervals even with a high reference frequency, a PLL circuit of the present invention includes variable frequency oscillation means for outputting an oscillation frequency signal, pulse train generating means receiving the oscillation frequency signal as a clock signal, for converting a train of n clocks to m pulses where n and m are positive integers, generating sequential pulses produced by arranging part of the m pulses so that they have non-uniform numbers of clocks, and outputting m periodical, sequential pulse trains so that the pulses having the non-uniform numbers of clocks are arranged differently, phase comparing means for outputting a phase error signal by determining a phase error between the reference frequency signal and the oscillation frequency signal based on the reference frequency signal and the m sequential pulse trains, and filtering means for filtering the phase error signal to produce a frequency control signal, and supplying the

Abstract: An amplifier for reducing an overshoot when an AC current is applied during class "C" amplification includes a transistor used to amplify an AC signal and a device that, just before an AC signal is applied to the transistor, sends a DC current to the transistor. As a result, when the AC signal is applied to the transistor, the junction temperature of the transistor is elevated to substantially the same level as operating junction temperature of the transistor.